ZHCSG75E April 2017 – April 2018 TUSB544
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1
TUSB544 Registers
- 7.6.1.1 GENERAL_4 Register (Offset = Ah) [reset = 1h]
- 7.6.1.2 GENERAL_5 Register (Offset = Bh) [reset = 0h]
- 7.6.1.3 GENERAL_6 Register (Offset = Ch) [reset = 0h]
- 7.6.1.4 DISPLAYPORT_1 Register (Offset = 10h) [reset = 0h]
- 7.6.1.5 DISPLAYPORT_2 Register (Offset = 11h) [reset = 0h]
- 7.6.1.6 DISPLAYPORT_3 Register (Offset = 12h) [reset = 0h]
- 7.6.1.7 DISPLAYPORT_4 Register (Offset = 13h) [reset = 0h]
- 7.6.1.8 DISPLAYPORT_5 Register (Offset = 1Bh) [reset = 0h]
- 7.6.1.9 USB3.1_1 Register (Offset = 20h) [reset = 0h]
- 7.6.1.10 USB3.1_2 Register (Offset = 21h) [reset = 0h]
- 7.6.1.11 USB3.1_3 Register (Offset = 22h) [reset = 0h]
- 7.6.1.12 USB3.1_4 Register (Offset = 23h) [reset = 23h]
- 7.6.1
TUSB544 Registers
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RNQ|40
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7.4.8 Operation Timing – Power Up
Figure 21. Power-Up Timing Table 9. Power-Up Timing
| PARAMETER | MIN | MAX | UNIT | |
|---|---|---|---|---|
| Td_pg | VCC (min) to Internal Power Good asserted high | 500 | µs | |
| Tcfg_su | CFG(1) pins setup (2) | 350 | µs | |
| Tcfg_hd | CFG(1) pins hold | 10 | µs | |
| TCTL_DB | CTL[1:0] and FLIP pin debounce | 16 | ms | |
| TVCC_RAMP | VCC supply ramp requirement | 100 | ms | |
(1) Following pins comprise CFG pins: I2C_EN, UEQ[1:0], DEQ[1:0], CFG[1:0], DIR[1:0],VIO_SEL, SLP_S0#, and SWAP.
(2) Recommend CFG pins are stable when VCC is at min.