ZHCS363L August 2011 – March 2017 TRF7970A
PRODUCTION DATA.
- 1器件概述
- 2修訂歷史記錄
- 3Device Characteristics
- 4Terminal Configuration and Functions
- 5Specifications
-
6Detailed Description
- 6.1 Overview
- 6.2 System Block Diagram
- 6.3 Power Supplies
- 6.4 Receiver – Analog Section
- 6.5 Receiver – Digital Section
- 6.6 Oscillator Section
- 6.7 Transmitter – Analog Section
- 6.8 Transmitter – Digital Section
- 6.9 Transmitter – External Power Amplifier and Subcarrier Detector
- 6.10 TRF7970A IC Communication Interface
- 6.11 TRF7970A Initialization
- 6.12 Special Direct Mode for Improved MIFARE Compatibility
- 6.13 NFC Modes
- 6.14
Direct Commands from MCU to Reader
- 6.14.1
Command Codes
- 6.14.1.1 Idle (0x00)
- 6.14.1.2 Software Initialization (0x03)
- 6.14.1.3 Initial RF Collision Avoidance (0x04)
- 6.14.1.4 Response RF Collision Avoidance (0x05)
- 6.14.1.5 Response RF Collision Avoidance (0x06, n = 0)
- 6.14.1.6 Reset FIFO (0x0F)
- 6.14.1.7 Transmission With CRC (0x11)
- 6.14.1.8 Transmission Without CRC (0x10)
- 6.14.1.9 Delayed Transmission With CRC (0x13)
- 6.14.1.10 Delayed Transmission Without CRC (0x12)
- 6.14.1.11 Transmit Next Time Slot (0x14)
- 6.14.1.12 Block Receiver (0x16)
- 6.14.1.13 Enable Receiver (0x17)
- 6.14.1.14 Test Internal RF (RSSI at RX Input With TX ON) (0x18)
- 6.14.1.15 Test External RF (RSSI at RX Input with TX OFF) (0x19)
- 6.14.1
Command Codes
- 6.15
Register Description
- 6.15.1 Register Preset
- 6.15.2 Register Overview
- 6.15.3
Detailed Register Description
- 6.15.3.1 Main Configuration Registers
- 6.15.3.2
Control Registers – Sublevel Configuration Registers
- 6.15.3.2.1 ISO/IEC?14443 TX Options Register (0x02)
- 6.15.3.2.2 ISO/IEC?14443 High-Bit-Rate and Parity Options Register (0x03)
- 6.15.3.2.3 TX Timer High Byte Control Register (0x04)
- 6.15.3.2.4 TX Timer Low Byte Control Register (0x05)
- 6.15.3.2.5 TX Pulse Length Control Register (0x06)
- 6.15.3.2.6 RX No Response Wait Time Register (0x07)
- 6.15.3.2.7 RX Wait Time Register (0x08)
- 6.15.3.2.8 Modulator and SYS_CLK Control Register (0x09)
- 6.15.3.2.9 RX Special Setting Register (0x0A)
- 6.15.3.2.10 Regulator and I/O Control Register (0x0B)
- 6.15.3.3
Status Registers
- 6.15.3.3.1 IRQ Status Register (0x0C)
- 6.15.3.3.2 Interrupt Mask Register (0x0D) and Collision Position Register (0x0E)
- 6.15.3.3.3 RSSI Levels and Oscillator Status Register (0x0F)
- 6.15.3.3.4 Special Functions Register (0x10)
- 6.15.3.3.5 Special Functions Register (0x11)
- 6.15.3.3.6 Adjustable FIFO IRQ Levels Register (0x14)
- 6.15.3.3.7 NFC Low Field Level Register (0x16)
- 6.15.3.3.8 NFCID1 Number Register (0x17)
- 6.15.3.3.9 NFC Target Detection Level Register (0x18)
- 6.15.3.3.10 NFC Target Protocol Register (0x19)
- 6.15.3.4 Test Registers
- 6.15.3.5 FIFO Control Registers
- 7Applications, Implementation, and Layout
- 8器件和文檔支持
- 9機(jī)械、封裝和可訂購信息
封裝選項
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RHB|32
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RHB|32
訂購信息
6.10.5 Serial Interface Communication (SPI)
When an SPI interface is used, I/O pins I/O_2, I/O_1, and I/O_0 must be hard wired according to Table 6-10. On power up, the TRF7970A looks for the status of these pins and then enters into the corresponding mode.
The serial communications work in the same manner as the parallel communications with respect to the FIFO, except for the following condition. On receiving an IRQ from the reader, the MCU reads the TRF7970A IRQ Status register to determine how to service the reader. After this, the MCU must to do a dummy read to clear the reader's IRQ status register. The dummy read is required in SPI mode because the reader's IRQ status register needs an additional clock cycle to clear the register. This is not required in parallel mode because the additional clock cycle is included in the Stop condition. When first establishing communications with the TRF7970A, the SOFT_INIT (0x03) and IDLE (0x00) commands should be sent first from the MCU (see Table 6-19).
The procedure for a dummy read is as follows (see Figure 6-17 and Figure 6-18):
- Start the dummy read:
- When using slave select (SS): set SS bit low.
- When not using SS: start condition is when Data Clock is high (see Table 6-10).
- Send address word to IRQ status register (0x0C) with read and continuous address mode bits set to 1 (see Table 6-10).
- Read 1 byte (8 bits) from IRQ status register (0x0C).
- Dummy-read 1 byte from register 0x0D (collision position and interrupt mask).
- Stop the dummy read:
- When using slave select (SS): set SS bit high.
- When not using SS: stop condition when Data Clock is high.
Figure 6-17 Procedure for Dummy Read
Figure 6-18 Example of Dummy Read Using SPI With SS