ZHCSIO9A August 2018 – June 2021 TPSM831D31
PRODUCTION DATA
The STATUS_CML command returns one byte with contents regarding communication, logic, or memory conditions.
The STATUS_CML command must be accessed through Read Byte/Write Byte transactions. The STATUS_CML command is shared between Channel A and Channel B. All transactions to this command affects both channels regardless of the PAGE command.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RW | RW | RW | RW | 0 | 0 | RW | 0 |
| IV_CMD | IV_DATA | PEC_FAIL | MEM | PRO_FAULT | Reserved | COM_FAIL | CML_OTHER |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | IV_CMD | RW | Current Status | Invalid or Unsupported Command Received 0: Latched flag indicating no invalid or unsupported command has been received. 1: Latched flag indicating an invalid or unsupported command has been received. |
| 6 | IV_DATA | RW | Current Status | Invalid or Unsupported Data Received 0: Latched flag indicating no invalid or unsupported data has been received. 1: Latched flag indicating an invalid or unsupported data has been received. |
| 5 | PEC_FAIL | RW | Current Status | Packet Error Check Failed 0: Latched flag indicating no packet error check has failed 1: Latched flag indicating a packet error check has failed |
| 4 | Reserved | R | 0 | Always set to 0. |
| 3 | MEM | RW | Current Status | Memory/NVM Error 0: Latched flag indicating no memory error has occurred 1: Latched flag indicating a memory error has occurred |
| 2 | Reserved | R | 0 | Always set to 0. |
| 1 | COM_FAIL | RW | Current Status | Other Communication Faults 0: Latched flag indicating no communication fault other than the ones listed in this table has occurred. 1: Latched flag indicating a communication fault other than the ones listed in this table has occurred. |
| 0 | CML_OTHER | R | 0 | Not supported and always set to 0. |
Per the description in the PMBus 1.3 specification, part II, TPSM831D31 does support clearing of status bits by writing to STATUS registers. Writing a 1 to any bit in this register attempts to clear it as a fault condition.