久久99精品久久久久久9,国产SUV精品一区二区五,色综合久久久久无码专区

ZHCSOW9C october 2022 – july 2023 TPSM82912 , TPSM82913 , TPSM82913E

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

RDU|28
- MPQF678

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

8.2.1 Design Requirements

The external components have to fulfill the needs of the application, but also meet the stability criteria of the control loop of the device. The device is optimized to work within a range of external components, and can be optimized for the following:

Efficiency
Output ripple
Component count
Lowest noise

Typical applications that have input voltages of ≤ 6 V use a 2.2-MHz switching frequency. Applications that have input voltages > 6 V can be optimized for efficiency using a 1-MHz switching frequency. In this case, the output voltage ripple doubles, which is typically acceptable when powering high speed ADCs. Optimization for powering clock and PLL circuits that need a 3.3-V output use a 2.2-MHz switching frequency, minimizing output voltage ripple and low frequency noise.

For the application cases that are not found in Table 8-2, there are two methods to design the TPSM8291x circuit. Section 8.2.2.1 uses Webench to design the circuit automatically or the calculations in Section 8.2.2.2 can be used instead.

Table 8-2 Typical Single L-C Filter Design Recommendations

DESIGN GOAL	V_IN	V_OUT	F_SW	OUTPUT CAPACITORS ^³
Typical	12 V^⁽¹⁾	≤ 2.0 V^⁽¹⁾	1 MHz	3 × 22 μF, 10 V, 0805
Higher efficiency (with higher ripple and noise)	12 V	2.0 V < V_OUT ≤ 3.3 V	1 MHz	3 × 22 μF, 10 V, 0805
Low ripple, noise PLL and Clock Supply	12 V	2.6 V ≤ V_OUT ≤ 3.3 V	2.2 MHz	3 × 22 μF, 10 V, 0805
Typical	12 V	> 3.3 V	2.2 MHz
Typical	5 V	≤ 3.3 V	2.2 MHz	3 × 22 μF, 10 V, 0805
Typical	5 V	> 3.3 V	2.2 MHz	1 × 47 μF, 1210 and 2 × 22 μF, 10 V, 0805

(1) The maximum input to output voltage difference is limited by the device maximum minimum on-time of 70 ns. This is especially important for input voltages above 12 V or output voltages below 1 V. See Section 8.2.2.2.1.

(2) For output capacitor part numbers, see Table 8-5.

The second stage L-C filter is optional, as the device can be used without this filter to achieve below 20-μV_RMS noise typically. A second stage filter is added to provide additional attenuation of the output voltage ripple. The output voltage is sensed after the second L-C filter by connecting the FB resistors to the second stage L-C filter capacitor. This action provides remote sense, minimizing output voltage drop due to the ferrite bead. Refer to Table 8-3 for second stage L-C filter recommendations based on the output voltage.

Table 8-3 Second Stage L-C (Ferrite Bead) Filter Design Recommendations

V_OUT (V)	FERRITE BEAD IMPEDANCE (AT 100 MHZ)^⁽²⁾	OUTPUT CAPACITORS ⁽¹⁾
≤ 3.3 V	8 Ω to 20 Ω	2 × 22 μF, 10 V, 0805
> 3.3 V	8 Ω to 20 Ω	3 × 22 μF, 10 V, 0805

(1) For output capacitor part numbers, see Table 8-5.

(2) For second stage L-C filter part numbers, see Table 8-5.