ZHCSOW9C october 2022 – july 2023 TPSM82912 , TPSM82913 , TPSM82913E
PRODUCTION DATA
The device has a power-good output. The PG pin goes high impedance once the FB pin voltage is above 95% of the nominal voltage, and is driven low after the voltage falls below typically 90% of the nominal voltage. Table 7-2 shows the typical PG pin logic. The PG pin is an open-drain output and is specified to sink up to 10 mA. The power-good output requires a pullup resistor connecting to any voltage rail less than 18 V. The PG signal can be used for sequencing of multiple rails by connecting to the EN pin of other converters. If not used, the PG pin can be left floating or connected to GND. PG has a deglitch time of typically 8 μs before going low.
| DEVICE STATE | PG LOGIC STATUS | ||
|---|---|---|---|
| HIGH IMPEDANCE | LOW | ||
| Enabled (EN/SYNC = High) | VFB ≥ VPG | √ | |
| VFB < VPG after tPG | √ | ||
| Shutdown (EN/SYNC = Low) | √ | ||
| UVLO | 0.7 V < VIN < VUVLO | √ | |
| Thermal Shutdown | TJ > TJSD | √ | |
| Power Supply Removal | VIN < 0.7 V | √ | |