A proper layout is critical for the operation of a
switched mode power supply, even more at high switching frequencies.
Therefore, the PCB layout of the TPSM82902 demands careful attention to ensure operation
and to get the performance specified. A poor layout can lead to
issues like poor regulation (both line and load), stability and
accuracy weaknesses, increased EMI radiation, bad thermal
performance, and noise sensitivity.
- See Figure 8-61 for the recommended layout of the TPSM82902, which is designed for common
external ground connections. TI recommends placing all
components as close as possible to the package pins. The
input and output capacitors placement specifically, must be
closest to the VIN, VOUT, and GND pins of the TPSM82902.
- Provide low
capacitive paths (with respect to all other nodes) for
traces with high dv/dt. Therefore, the input and output
capacitance must be placed as close as possible to the IC
pins and parallel wiring over long distances as well as
narrow traces must be avoided. Loops which conduct an
alternating current must outline an area as small as
possible, as this area is proportional to the energy
radiated.
- Sensitive nodes
like FB needs to be connected with short wires and not
nearby high dv/dt signals. As it carries information about
the output voltage, it must be connected as close as
possible to the actual output voltage (at the output
capacitor). The capacitor on the SS/TR pin as well as the FB
resistors, R1 and R2, must be kept close to the module and
connect directly to those pins and the system ground plane.
The same applies to VSET resistor if VSET is used to scale
the output voltage.
- The package uses
the pins for power dissipation. Thermal vias on the VIN,
VOUT, and GND pins help to spread the heat through the
PCB.
- In case of the
EN, and MODE/S-CONF need to be tied to the input supply
voltage at VIN, the connection must be made
directly at the input capacitor as indicated in the
schematics.
- The SW/NC pin must not be connected to any other traces. For
best practice, this pin must be left floating. If the pin
is soldered to PCB copper, the pour needs to be: as small as
possible, no inner layer connections, no vias, electrically
floating, and limited to the pin area as possible.
- Refer to Figure 8-61 for an example of component placement, routing and
thermal design. The recommended layout is implemented on the
EVM and shown in its user's guide.