ZHCSMK6D September 2021 – November 2024 TPSM82864A , TPSM82866A
PRODMIX
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Device Options
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
7.4.3 Power Good (PG)
The device has an open-drain power-good pin, which is specified to sink up to 2 mA. The power-good output requires a pullup resistor connected to any voltage rail less than 5.5 V. The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters. Leave the PG pin unconnected when not used. Table 7-1 shows the typical PG pin logic.
Table 7-1 PG Pin Logic
The PG pin has a 34-μs delay time on the falling edge and a 34-μs delay before PG goes high. See Figure 7-3.| DEVICE CONDITIONS | LOGIC STATUS | ||
|---|---|---|---|
| HIGH IMPEDANCE | LOW | ||
| Enable | 0.9 × VOUT_NOM ≤ VVOUT ≤ 1.1 × VOUT_NOM | √ | |
| VVOUT < 0.9 × VOUT_NOM or VVOUT > 1.1 × VOUT_NOM | √ | ||
| Shutdown | EN = low | √ | |
| Thermal shutdown | TJ > TJSD | √ | |
| UVLO | 1.8 V < VIN < VUVLO | √ | |
| Power supply removal | VIN < 1.8 V | undefined | |
Figure 7-3 Power-Good Transient and Delay
Behavior