ZHCSHU5A July 2017 – March 2018 TPSM82480
PRODUCTION DATA.
- 1 選項
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.4.3 Minimum Duty Cycle and 100% Mode Operation
The minimum on-time, which is typically 70ns, normally determines a limit on the minimum operating duty cycle. The calculation is:
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However, a frequency foldback lowers the switching frequency depending on the duty cycle and ensures proper regulation for every duty cycle.
There is no limit towards maximum duty cycle. When the input voltage becomes close to the output voltage, the device enters automatically 100% duty cycle mode and both high-side FETs switch on as long as VOUT remains below the regulation setpoint. In this case, the voltage drop across the high-side FETs and the inductors determines the output voltage level. An estimate for the minimum input voltage to maintain output voltage regulation is:
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Where the maximum DCR of the inductors is 27mΩ.
In 100% duty cycle mode, the low-side FETs are switched off. The typical quiescent current in 100% mode is
3.5 mA.