ZHCSLX4A October 2020 – December 2020 TPSM41615
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Setting the Output Voltage
- 7.3.2 RS+/RS- Remote Sense Function
- 7.3.3 Ramp Select (RAMP and RAMP_SEL)
- 7.3.4 Switching Frequency (RT)
- 7.3.5 Synchronization (SYNC)
- 7.3.6 Stand-alone/Stackable Operation
- 7.3.7 Improved Transient Performance versus Fixed Frequency (Stand-alone Operation Only)
- 7.3.8 Output On/Off Enable (EN)
- 7.3.9 Power Good (PGOOD)
- 7.3.10 Soft-Start Operation
- 7.3.11 Input Capacitor Selection
- 7.3.12 Output Capacitor Selection
- 7.3.13 Current Limit (ILIM)
- 7.3.14 Safe Start-up into Pre-Biased Outputs
- 7.3.15 Overcurrent Protection
- 7.3.16 Output Overvoltage and Undervoltage Protection
- 7.3.17 Overtemperature Protection
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- MOV|69
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7.3.6.1.3 Configuration 1: Dual Phase, Primary Sync-Out Clock to Secondary
- Direct SYNC, VSHARE, and ISHARE connections between primary and secondary
- Switching frequency is set by RT pin of primary, and pass to secondary through SYNC pin. SYNC pin of primary will be configured as sync out by its MODE pin.
- Secondary receives clock from SYNC pin. Its RT pin determines the sync point for clock phase shift.
Figure 7-4 2-Phase Stackable, 180° Phase Shift: Primary
Sync-Out Clock to Secondary