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ZHCSPJ0C april 2022 – august 2023 TPSI3050

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

DWZ|8
- MPSS140

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6.9 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted). Typicals at T_A = 25℃. C_VDDP = 220 nF, C_DIV1 = C_DIV2 = 3.3 nF, C_VDRV= 100 pF, R_PXFR = 7.32 k? ± 1%

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
COMMON
V_{VDDP_UV_R}	VDDP undervoltage threshold rising	VDDP rising	2.50	2.70	2.90	V
V_{VDDP_UV_F}	VDDP undervoltage threshold falling	VDDP falling	2.35	2.55	2.75	V
V_{VDDP_UV_HYS}	VDDP undervoltage threshold hysterisis			75		mV
TSD	Temperature shutdown			173		℃
TSDH	Temperature shutdown hysteresis			32		℃
V_{VDDH_UV_R}	VDDH undervoltage threshold rising	VDDH rising.	8.3	8.6	9.0	V
V_{VDDH_UV_F}	VDDH undervoltage threshold falling TPSI3050 only.	VDDH falling.	6.3	6.6	6.9	V
V_{VDDH_UV_F}	VDDH undervoltage threshold falling TPSI3050S only. One-shot enable mode only available in three-wire operation.	VDDH falling.	7.2	7.5	7.8	V
V_{VDDH_UV_HYS}	VDDH undervoltage threshold hysterisis TPSI3050 only.			2		V
V_{VDDH_UV_HYS}	VDDH undervoltage threshold hysterisis TPSI3050S only.			1.1		V
I_{Q_VDDH}	Internal quiescent current of VDDH supply.			36		μA
R_{DSON_VDRV}	Driver on resistance in low state	Force V_VDDH= 10 V, sink I_VDRV = 50 mA.		1.7		?
R_{DSON_VDRV}	Driver on resistance in high state	Force V_VDDH= 10 V, source I_VDRV = 50 mA.		2.5		?
I_{VDRV_PEAK}	VDRV peak output current during rise	V_VDDH in steady state, transition EN from low to high, measure peak current.		1.5		A
I_{VDRV_PEAK}	VDRV peak output current during fall	V_VDDH in steady state, transition EN from high to low, measure peak current.		3		A
CMTI	Common-mode transient immunity	\|V_CM\| = 1000 V	100			V/ns
TWO-WIRE MODE
V_{IH_EN}	Minimum voltage on EN to be detected as a valid logic high		6.5			V
V_{IL_EN}	Maximum voltage on EN to be detected as a valid logic low				2.0	V
I_{EN_START}	Enable current at startup	EN = 0 V → 6.5 V		27		mA
I_EN	Enable current steady state	EN = 6.5 V, R_PXFR= 7.32 k?, R_PXFR ≥100 k? or R_PXFR ≤1 k?, V_VDDH in steady state.		1.9		mA
I_EN	Enable current steady state	EN = 6.5 V, R_PXFR = 20 k?, V_VDDH in steady state.		6.8		mA
V_{VDDP_RIPPLE}	VDDP output voltage ripple	EN = 6.5 V, V_VDDH in steady state.		600		mV
V_VDDH	VDDH output voltage	EN = 6.5 V, V_VDDH in steady state.	9.4	10.2	11	V
V_{VDRV_H}	VDRV output voltage driven high	EN = 6.5 V, V_VDDH in steady state, no DC loading.	9.4	10.2	11	V
V_{VDRV_L}	VDRV output voltage driven low	EN = 6.5 V → 0 V, V_VDDH in steady state, sink 10 mA load.			0.1	V
V_{VDDM_IAUX}	Average VDDM voltage when sourcing external current	EN = 6.5 V, steady state. R_PXFR= 7.32 k?, R_PXFR ≥ 100 k? or R_PXFR ≤ 1 k?, C_DIV1 = C_DIV2 = 220 nF, source 0.4 mA from VDDM, measure VDDM voltage.	4.6		5.5	V
V_{VDDM_IAUX}	Average VDDM voltage when sourcing external current	EN = 6.5 V, steady state. R_PXFR= 20 k?, C_DIV1 = C_DIV2 = 220 nF, source 1.7 mA from VDDM, measure VDDM voltage.	4.6		5.5	V
THREE-WIRE MODE
V_{IH_EN}	Minimum voltage on EN to be detected as a valid logic high. V_IH(min) = 0.7 x V_VDDP	V_VDDP = 3 V	2.1			V
V_{IH_EN}		V_VDDP = 5.5 V	3.85			V
V_{IL_EN}	Maximum voltage on EN to be detected as a valid logic low	V_VDDP = 3 V			0.9	V
V_{IL_EN}	Maximum voltage on EN to be detected as a valid logic low	V_VDDP = 5.5 V			1.65	V
I_VDDP	VDDP average current in steady state	EN = 3.3 V, V_VDDP = 3.3 V, R_PXFR = 7.32 k?, R_PXFR ≥ 100 k? or R_PXFR ≤ 1 k?, V_VDDH in steady state, measure I_VDDP.		3.1		mA
		EN = 3.3 V, V_VDDP = 3.3 V, R_PXFR = 20 k? V_VDDH in steady state, measure I_VDDP.		26		mA
		EN = 5 V, V_VDDP = 5 V, R_PXFR = 7.32 k?, R_PXFR ≥ 100 k? or R_PXFR ≤ 1 k?, V_VDDH in steady state, measure I_VDDP.		4.8		mA
		EN = 5 V, V_VDDP = 5 V, R_PXFR = 20 k?, V_VDDH in steady state, measure I_VDDP.		37		mA
V_{VDDM_IAUX}	Average VDDM voltage when sourcing external current	V_VDDP = 3.3 V, EN = 0 V, steady state, R_PXFR = 7.32 k?, C_DIV1 = C_DIV2 = 220 nF, source 0.4 mA from VDDM, measure V_VDDM.	4.6		5.5	V
		V_VDDP = 5.0 V, EN = 0 V, steady state, R_PXFR = 7.32 k?, C_DIV1 = C_DIV2 = 220 nF, source 1.0 mA from VDDM, measure V_VDDM.	4.6		5.5	V
		V_VDDP = 3.3 V, EN = 0 V, steady state, R_PXFR =20 k?, C_DIV1 = C_DIV2 = 220 nF, source 5.5 mA from VDDM, measure V_VDDM.	4.6		5.5	V
		V_VDDP = 5.0 V, EN = 0 V, steady state, R_PXFR = 20 k?, C_DIV1 = C_DIV2 = 220 nF, source 10 mA from VDDM, measure V_VDDM.	4.6		5.5	V
V_VDDH	VDDH output voltage	V_VDDP = 3.0 V, EN = 3.0 V, V_VDDH in steady state.	9.4	10.2	11	V
V_{VDRV_H}	VDRV output voltage driven high	V_VDDP = 3.0 V, EN = 3.0 V, V_VDDH in steady state, no DC loading.	9.4	10.2	11	V
V_{VDRV_L}	VDRV output voltage driven low	V_VDDP = 3.0 V, EN = 0 V, V_VDDH in steady state, VDRV sinking 10 mA.			0.1	V