Designers must pay close attention to
PCB layout to achieve optimum performance for the TPSI3050. Some key guidelines are:
- Component placement:
- Place the driver as close
as possible to the power semiconductor to reduce the parasitic
inductance of the gate loop on the PCB traces.
- Connect low-ESR and
low-ESL capacitors close to the device between the VDDH and VDDM pins
and the VDDM and VSSS pins to bypass noise and to support high peak
currents when turning on the external power transistor.
- Connect low-ESR and
low-ESL capacitors close to the device between the VDDP and VSSP
pins.
- Minimize parasitic
capacitances on the RPXFR pin.
- Grounding considerations:
- Limit the high peak
currents that charge and discharge the transistor gates to a minimal
physical area. This limitation decreases the loop inductance and
minimizes noise on the gate terminals of the transistors. Place the gate
driver as close as possible to the transistors.
- Connect the driver VSSS
to the Kelvin connection of MOSFET source or IGBT emitter. If the power
device does not have a split Kelvin source or emitter, connect the VSSS
pin as close as possible to the source or emitter terminal of the power
device package to separate the gate loop from the high power switching
loop.
- High-voltage considerations:
- To ensure isolation
performance between the primary and secondary side, avoid placing any
PCB traces or copper below the driver device. TI recommends a PCB cutout
or groove to prevent contamination that can compromise the isolation
performance.
- Thermal considerations:
- Proper PCB layout can
help dissipate heat from the device to the PCB and minimize
junction-to-board thermal impedance (θJB).
- If the system has
multiple layers, TI also recommends connecting the VDDH and VSSS pins to
internal ground or power planes through multiple vias of adequate size.
These vias must be located close to the IC pins to maximize thermal
conductivity. However, keep in mind that no traces or coppers from
different high voltage planes are overlapping.