ZHCSLG9A October 2020 – August 2024 TPS99000S-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 Electrical Characteristics—Transimpedance Amplifier Parameters
- 5.6 Electrical Characteristics—Digital to Analog Converters
- 5.7 Electrical Characteristics—Analog to Digital Converter
- 5.8 Electrical Characteristics—FET Gate Drivers
- 5.9 Electrical Characteristics—Photo Comparator
- 5.10 Electrical Characteristics—Voltage Regulators
- 5.11 Electrical Characteristics—Temperature and Voltage Monitors
- 5.12 Electrical Characteristics—Current Consumption
- 5.13 Power-Up Timing Requirements
- 5.14 Power-Down Timing Requirements
- 5.15 Timing Requirements—Sequencer Clock
- 5.16 Timing Requirements—Host and Diagnostic Port SPI Interface
- 5.17 Timing Requirements—ADC Interface
- 5.18 Switching Characteristics
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1
Illumination Control
- 6.3.1.1 Illumination System High Dynamic Range Dimming Overview
- 6.3.1.2 Illumination Control Loop
- 6.3.1.3 Continuous Mode Operation
- 6.3.1.4
Discontinuous Mode Operation
- 6.3.1.4.1 Discontinuous Mode Pulse Width Limit
- 6.3.1.4.2 COMPOUT_LOW Timer in Discontinuous Operation
- 6.3.1.4.3 Dimming Within Discontinuous Operation Range
- 6.3.1.4.4 Multiple Pulse Heights to Increase Bit Depth
- 6.3.1.4.5 TIA Gain Adjustment
- 6.3.1.4.6 Current Limit in Discontinuous Mode
- 6.3.1.4.7 CMODE Big Cap Mode in Discontinuous Operation
- 6.3.2 Over-Brightness Detection
- 6.3.3 Analog to Digital Converter
- 6.3.4 Power Sequencing and Monitoring
- 6.3.5 DMD Mirror Voltage Regulator
- 6.3.6 Low Dropout Regulators
- 6.3.7 System Monitoring Features
- 6.3.8 Communication Ports
- 6.3.1
Illumination Control
- 6.4 Device Functional Modes
- 6.5 Register Maps
- 7 Application and Implementation
- 8 Power Supply Recommendations
- 9 Layout
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
- PZP|100
散熱焊盤機械數據 (封裝 | 引腳)
- PZP|100
訂購信息
5.16 Timing Requirements—Host and Diagnostic Port SPI Interface
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| tSPICPER | SPI CLK Cycle Time | 31 | 33 | ns | |
| tSPICHIGH | SPI CLK High Time | 10 | ns | ||
| tSPICLOW | SPI CLK Low Time | 10 | ns | ||
| tSPIDOUT | CLK Falling to DOUT | 0 | 15 | ns | |
| tSSSETUP | SPI SS_Z to CLK Rising Setup Time | 5 | ns | ||
| tSSHOLD | SPI CLK Rising to SS_Z Hold Time | 5 | ns | ||
| tDINSETUP | SPI DIN to CLK Rising Setup Time | 5 | ns | ||
| tDINHOLD | SPI CLK Rising to DIN Hold Time | 5 | ns | ||
Figure 5-4 DLPC23xS-Q1 Diagnostic Interface Timing
Figure 5-5 Chip Select Setup and Hold
Timing