SLUSE50 November 2023 TPS92642-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| INPUT VOLTAGE (VIN) | ||||||
| VDO | LDO dropout voltage | IVCC = 20 mA, VVIN = 5 V | 315 | mV | ||
| ISW | Input switching current | 10 | 17.6 | mA | ||
| IOP | Input operating current | Not switching, VIADJ = VVCC | 2 | 4 | mA | |
| BIAS SUPPLY (VCC) | ||||||
| VCC(UVLO-RISE) | Rising threshold | VCC rising threshold, VVIN = 8 V | 4.40 | 4.58 | V | |
| VCC(UVLO-FALL) | Falling threshold | VCC falling threshold, VVIN = 8 V | 3.9 | 4.2 | V | |
| VCC(UVLO-HYS) | Hysteresis | 200 | mV | |||
| VCC(REG) | Regulation voltage | No Load | 4.75 | 5.00 | 5.25 | V |
| ICC(LIMIT) | Supply current Limit | VVCC = 0 V | 45 | 56 | 76 | mA |
| HIGH-SIDE FET (SW, BOOT) | ||||||
| RDS(ON-HS) | High-side MOSFET on resistance | ILED = 100 mA | 65 | 130 | mΩ | |
| VBST(UV) | Bootstrap gate drive UVLO | V(BST-SW) rising | 3.24 | 3.4 | 3.54 | V |
| VBST(HYS) | Bootstrap gate drive UVLO hysteresis | Hysteresis | 175 | 207 | 240 | mV |
| IQ(BST) | Bootstrap pin quiescent current | VSW = 0V, VUDIM = 0 V, VBOOT = 5 V | 215 | 280 | 350 | μA |
| LOW-SIDE FET (SW) | ||||||
| RDS(ON-LS) | Low-side MOSFET on resistance | ILED = 100 mA | 67 | 130 | mΩ | |
| HIGH SIDE FET CURRENT LIMIT | ||||||
| ILIM(HS) | High-side current limit threshold | 6.1 | 8.6 | 10.3 | A | |
| t(HS-BLANK) | High-side current sense blanking period | 60 | ns | |||
| LOW SIDE FET CURRENT LIMIT | ||||||
| ISINK(LS) | Sinking current limit | 2.0 | 3.2 | 4.3 | A | |
| tBLANK | Blanking time | 71 | ns | |||
| ERROR AMPLIFIER (CSP, CSN, COMP) | ||||||
| V(CSP-CSN) | Current sense threshold | VIADJ = VCC, VCSP = 3 V, ICOMP = 0 V | 168 | 175 | 182 | mV |
| VIADJ = 2.1 V, VCSP = 3 V, ICOMP = 0 V | 150 | mV | ||||
| ICSP | CSP bias current | VIADJ = 150 mV | 10 | μA | ||
| gM | Transconductance | 450 | μA/V | |||
| ICOMP(SRC) | COMP current source capacity | VIADJ = 2.5 V, V(CSP-CSN) = 0 V | 200 | μA | ||
| ICOMP(SINK) | COMP current sink capacity | VIADJ = 150 mV, V(CSP-CSN) = 300 mV | 140 | μA | ||
| VCOMP(RISE) | COMP startup threshold | Rising | 2.45 | V | ||
| VCOMP(HYS) | COMP startup comparator hysteresis | 440 | mV | |||
| EA(BW) | Bandwidth | Unity gain bandwidth | 3 | MHz | ||
| ICOMP(LKG) | Comp leakage current | VUDIM = 0 V | 2.5 | nA | ||
| VCOMP(RST) | COMP pin reset voltage | VVCC dropping from 5 V to 0 V | 100 | mV | ||
| RCOMP(DCH) | COMP discharge FET resistance | 230 | Ω | |||
| VCOMP(OV) | COMP overvoltage protection threshold | 2.9 | 3.2 | V | ||
| VCOMP(OV-HYS) | COMP overvoltage protection hysteresis | 60 | mV | |||
| VCSP(SHORT) | Output short circuit detection threshold | Falling | 1.5 | V | ||
| Rising | 1.6 | V | ||||
| ANALOG ADJUST INPUT (IADJ) | ||||||
| VIADJ(CLAMP) | IADJ internal clamp voltage | 2.45 | V | |||
| VIADJ(DIS) | Disable threshold voltage |
Rising | 133 | mV | ||
| VIADJ(DIS) | Disable threshold voltage | Falling | 100 | mV | ||
| VALLEY CURRENT COMPARATOR | ||||||
| gM(LV) | Level shift amplifier transconductance | 50 | μA/V | |||
| tDEL | V(CSP-CSN) falling to gate rising delay | 65 | ns | |||
| ON-TIME GENERATOR (RON) | ||||||
| tON(MIN) | Minimum on-time | 85 | 101 | 117 | ns | |
| tON | Programmed on-time | VVIN = 14 V, VCSP = 5 V, RON = 35 kΩ | 150 | ns | ||
| VVIN = 10 V, VCSP = 8 V, RON = 35 kΩ | 336 | ns | ||||
| VVIN = 14 V, VCSP = 3 V, RON = 400 kΩ | 0.95 | μs | ||||
| VVIN = 10 V, VCSP = 8 V, RON = 400 kΩ | 3.55 | μs | ||||
| MINIMUM OFF-TIME | ||||||
| tOFF(MIN) | Minimum off-time | V(CSP-CSN) = 0 V, VCOMP = 2.5 V | 63 | 78 | 93 | ns |
| PWM DIMMING and PROGRAMMABLE UVLO INPUT (UDIM) | ||||||
| IUDIM(DO) | UDIM source current (UVLO hysteresis) | VUDIM > 2.45 V | 6.5 | 10 | 13 | μA |
| VUDIM(EN,RISE) | Undervoltage lockout rising threshold | VUDIM rising | 1.22 | 1.27 | V | |
| VUDIM(EN,FALL) | Undervoltage lockout falling threshold | VUDIM falling | 1.075 | 1.120 | V | |
| tUDIM(RISE) | UDIM to SW pin rising delay | 1200 | ns | |||
| tUDIM(FALL) | UDIM pin SW pin falling delay | 105 | ns | |||
| DUTY CYCLE LIMIT | ||||||
| RPLMT(PU) | PLMT Pull-Up Resistor | 19.2 | 22.7 | 28.3 | kΩ | |
| RPLMT(PD) | PLMT Pull-Down Resistor | 75.0 | 91.8 | 110.0 | kΩ | |
| RPLMT(DIS) | PLMT Discharge Resistor | 48 | Ω | |||
| VPLMT(PK) | PLMT Peak Voltage | 2.340 | 2.439 | 2.540 | V | |
| VPLMT(VAL) | PLMT Valley Voltage | 786 | 819 | 851 | mV | |
| FAULT INDICATION (nFLT) | ||||||
| R(FLT) | Fault pin pull-down resistance | IFLT = 20 mA | 2.5 | 7 | Ω | |
| TOC | Hiccup retry delay time | 5.5 | ms | |||
| TUC(BLANK) | Undercurrent reporting blanking period | 20 | μs | |||
| IFLT(LKG) | Fault pin leakage current | 100 | nA | |||
| THERMAL SHUTDOWN | ||||||
| TSD | Thermal shutdown threshold | 175 | °C | |||
| TSD(HYS) | Thermal shutdown hysteresis | 15 | °C | |||