ZHCSLI9A December 2021 – June 2022 TPS92623-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| BIAS | ||||||
| V(POR_rising) | Supply voltage POR rising threshold | 3.6 | 4.0 | V | ||
| V(POR_falling) | Supply voltage POR falling threshold | 3.0 | 3.4 | V | ||
| I(Quiescent) | Device standby ground current | PWM = HIGH | 1.6 | 2.5 | mA | |
| I(FAULT) | Device supply current in fault mode | PWM = HIGH, FAULT externally pulled LOW | 0.21 | 0.350 | 0.45 | mA |
| LOGIC INPUTS (DIAGEN, PWM) | ||||||
| VIL(DIAGEN) | Input logic-low voltage, DIAGEN | 1.045 | 1.1 | 1.155 | V | |
| VIH(DIAGEN) | Input logic-high voltage, DIAGEN | 1.14 | 1.2 | 1.26 | V | |
| VIL(PWM) | Input logic-low voltage, PWM | 1.045 | 1.1 | 1.155 | V | |
| VIH(PWM) | Input logic-high voltage, PWM | 1.14 | 1.2 | 1.26 | V | |
| CONSTANT-CURRENT DRIVER | ||||||
| I(OUTx_Tot) | Device output-current for each channel | 100% duty cycle | 5 | 150 | mA | |
| V(CS_REG) | Sense-resistor regulation voltage | TA = –40°C to +125°C | 144 | 150 | 156 | mV |
| ALL ΔV(CS_c2c) | Channel to channel mismatch | ΔV(CS_c2c) = 1 – V(CS_REGx)/Vavg(CS_REG) | –3 | +3 | % | |
| ALL ΔV(CS_d2d) | Device to device mismatch | ΔV(CS_d2d) = 1 – Vavg(CS_REG)/Vnom(CS_REG) | –4 | +4 | % | |
| R(CS_REG) | Sense-resistor range | 0.96 | 31.2 | Ω | ||
| V(DROPOUT) | Voltage dropout from INx to OUTx, RESx open | current setting of 100 mA | 200 | 400 | mV | |
| current setting of 150 mA | 300 | 600 | ||||
| Voltage dropout from INx to RESx, OUTx open | current setting of 100 mA | 280 | 600 | mV | ||
| current setting of 150 mA | 400 | 900 | ||||
| I(RESx) | Ratio of RESx current to total current | I(RESx)/I(OUTx_Tot), V(INx) – V(RESx) > 1 V | 95 | % | ||
| DIAGNOSTICS | ||||||
| V(OPEN_th_rising) | LED open rising threshold, V(IN) – V(OUT) | 180 | 300 | 420 | mV | |
| V(OPEN_th_falling) | LED open falling threshold, V(IN) – V(OUT) | 450 | mV | |||
| V(SG_th_rising) | Channel output short-to-ground rising threshold | 1.14 | 1.2 | 1.26 | V | |
| V(SG_th_falling) | Channel output short-to-ground falling threshold | 0.855 | 0.9 | 0.945 | V | |
| I(Retry_OUTx) | Channel output V(OUT) short-to-ground retry current | 0.64 | 1.08 | 1.528 | mA | |
| I(Retry_RESx) | Channel output V(OUT) short-to-ground retry current | 0.64 | 1.08 | 1.528 | mA | |
| FAULT | ||||||
| VIL(FAULT) | Logic input low threshold | 0.7 | V | |||
| VIH(FAULT) | Logic input high threshold | 2 | V | |||
| t(FAULT_rising) | Fault detection rising edge deglitch time | 10 | μs | |||
| t(FAULT_falling) | Fault detection falling edge deglitch time | 20 | μs | |||
| I(FAULT_pulldown) | FAULT internal pulldown current | V(FAULT) = 0.4 V | 2 | 3 | 4 | mA |
| I(FAULT_pullup) | FAULT internal pullup current | 6 | 10 | 14 | μA | |
| I(FAULT_leakage) | FAULT leakage current | V(FAULT) = 20 V | 0.01 | 2 | μA | |
| TIMING | ||||||
| t(PWM_delay_rising) | PWM rising edge delay to 10% of output current, t1 as shown in Figure 7-1 | V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNSx) = 1 ? and R(RESx) = 56 ? | 3 | μs | ||
| V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNSx) = 30 ? and R(RESx) = 56 ? | 3 | μs | ||||
| t(PWM_delay_falling) | PWM falling edge delay to 90% of output current, t2 as shown in Figure 7-1 | V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNSx) = 1 ? and R(RESx) = 56 ? | 3.8 | μs | ||
| V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNSx) = 30 ? and R(RESx) = 56 ? | 3.8 | μs | ||||
| t(Current_rising) | Output current rising from 10% to 90%, t3 as shown in Figure 7-1 | V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNSx) = 1 ? and R(RESx) = 56 ? | 2 | μs | ||
| V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNSx) = 30 ? and R(RESx) = 56 ? | 1 | μs | ||||
| t(Current_falling) | Output current falling from 90% to 10%, t4 as shown in Figure 7-1 | V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNSx) = 1 ? and R(RESx) = 56 ? | 5 | μs | ||
| V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNSx) = 30 ? and R(RESx) = 56 ? | 0.2 | μs | ||||
| t(STARTUP) | SUPPLY rising edge to 10% output current, t5 as shown in Figure 7-1 | V(SUPPLY) = 12 V, V(OUT) = 6 V, V(CS_REG) = 150 mV, R(SNSx) = 1 ? and R(RESx) = 56 ? | 85 | μs | ||
| t(OPEN_deg) | LED-open fault detection deglitch time, t6 as shown in Figure 7-4 | 125 | μs | |||
| t(SG_deg) | Output short-to-ground detection deglitch time, t7 as shown in Figure 7-3 | 125 | μs | |||
| t(Recover_deg) | Open and Short fault recovery deglitch time, t8 as shown in Figure 7-3 and Figure 7-4 | 125 | μs | |||
| t(FAULT_recovery) | Fault recovery delay time, t9 as shown in Figure 7-3 and Figure 7-4 | 50 | μs | |||
| t(TSD_deg) | Thermal over temperature deglitch time | 50 | μs | |||
| THERMAL PROTECTION | ||||||
| T(TSD) | Thermal shutdown junction temperature threshold | 157 | 172 | 187 | °C | |
| T(TSD_HYS) | Thermal shutdown junction temperature hysteresis | 15 | °C | |||