10.3.1 DCS-Control™

TI's DCS-Control™ (Direct Control with Seamless Transition into Power Save Mode) is an advanced regulation topology, which combines the advantages of hysteretic and voltage mode control. Characteristics of DCS-Control™ are excellent AC load regulation and transient response, low output ripple voltage and a seamless transition between PFM and PWM mode operation. DCS-Control™ includes an AC loop which senses the output voltage (VOUT pin) and directly feeds the information to a fast comparator stage. This comparator sets the switching frequency, which is constant for steady state operating conditions, and provides immediate response to dynamic load changes. In order to achieve accurate DC load regulation, a voltage feedback loop is used.

The DCS-Control™ topology supports PWM (Pulse Width Modulation) mode for medium and high load conditions and Power Save Mode at light loads. During PWM mode, it operates in continuous conduction. The switching frequency goes up to 1.7MHz with a controlled frequency variation depending on the input voltage. If the load current decreases, the converter seamlessly enters Power Save Mode to maintain high efficiency down to very light loads. In Power Save Mode, the switching frequency varies nearly linearly with the load current. Since DCS-Control™ supports both operation modes within one single building block, the transition from PWM to Power Save Mode is seamless without effects on the output voltage. The TPS82740 offers both excellent DC voltage and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with RF circuits. At high load currents, the converter operates in quasi fixed frequency PWM mode operation and at light loads in PFM (Pulse Frequency Modulation) mode to maintain highest efficiency over the full load current range. In PFM Mode, the device generates a single switching pulse to ramp up the inductor current and recharge the output capacitor, followed by a sleep period where most of the internal circuits are shutdown to achieve the lowest quiescent current. During this time, the load current is supported by the output capacitor. The duration of the sleep period depends on the load current and the inductor peak current.

During the sleep periods, the quiescent current of the TPS82740 is reduced to 360nA. This low quiescent current consumption is achieved by an ultra low power voltage reference, an integrated high impedance (typ. 50MΩ) feedback divider network and an optimized DCS-Control™ block.

10.3.2 LOAD Switch

The LOAD pin can be used to power an additional, temporarily used sub-system. If the CTRL pin is set high, the LOAD pin is connected to the VOUT pin via an integrated load switch. The load switch is slew rate controlled to support soft switching and not impacting the regulated output VOUT. If the CTRL pin is set to low, the LOAD pin is disconnected from the VOUT pin and internally connected to GND by an internal discharge switch. The CTRL pin can be controlled by a micro controller and must be terminated. With CTRL pin high, the quiescent current is increased to improve the transient response.

10.3.3 Output Voltage Selection (VSEL1, VSEL2, VSEL3)

The TPS82740 provides an integrated, high impedance (typ. 50MΩ) feedback resistor divider network which is programmed by the pins VSEL1-3. The TPS82740A supports an output voltage range of 1.8V to 2.5V in 100mV steps, while the TPS82740B supports an output voltage range from 2.6V to 3.3V in 100mV steps. The output voltage can be changed during operation and supports a simple dynamic output voltage scaling, shown in Figure 44. The output voltage is programmed according to Table 2 and Table 3.

10.3.4 Output Discharge Function (VOUT and LOAD)

Both the VOUT pin and the LOAD pin feature a discharge circuit to connect each rail to GND, once they are disabled. This feature prevents residual charge voltages on capacitors connected to these pins, which may impact proper power up of the main- and sub-system. With the CTRL pin pulled low, the discharge circuit at the LOAD pin activates. With the EN pin pulled low, the discharge circuit at the pin VOUT activates.

10.3.5 Internal Current Limit

The TPS82740 integrates a current limit in the high side, as well as in the low side MOSFETs to protect the device against overload or short circuit conditions. The peak current in the switches is monitored cycle by cycle. If the high side MOSFET current limit is reached, the high side MOSFET is turned off and the low side MOSFET is turned on until the current decreases below the low side MOSFET current limit.

10.3.6 CTRL / DVS (Dynamic Voltage Scaling TPS62741)

In TPS62741, the CTRL pin controls beside the load switch as well Dynamic Voltage Scaling. The CTRL pin selects between two different voltage setting banks. The voltage of each bank are set with the VSEL pins 1-4 according to .

The output LOAD is controlled with the CTRL pin. The pin is internally connected either to VOUT pin or GND and can be used to power up/down temporarily used external circuits to reduce leakage current consumption of the system.

10.4.1 Enable / Shutdown

The TPS82740 is activated when the EN pin is set high. For proper operation, the pin must be terminated and must not be left floating. With the EN pin set low, the device enters shutdown mode with less than typ. 70nA current consumption.

10.4.2 Softstart

When the device is enabled, the internal reference is powered up and after the startup delay time t_{Startup_delay} has expired, the device enters softstart, starts switching and ramps up the output voltage. During softstart, the device operates with a reduced current limit, I_{LIM_softstart}, of typ. 1/3 of the nominal current limit. This reduced current limit is active during the time t_Softstart. The current limit is increased to its nominal value, I_LIMF, once this time has expired or the nominal output voltage is reached.

10.4.3 POWER GOOD OUTPUT (PG)

The Power Good comparator features an open drain output. The PG comparator is active with EN pin set to high and V_IN is above the threshold V_{TH_UVLO+}. It is driven to high impedance once V_OUT trips the threshold V_{TH_PG+} for rising V_OUT. The output is pulled to low level once V_OUT falls below the PG hysteresis, V_{PG_hys}. The output is also pulled to low level in case the input voltage V_IN falls below the undervoltage lockout threshold V_{TH_UVLO-} or the device is disabled with EN = low. The power good output (PG) can be used as an indicator for the system to signal that the converter has started up and the output voltage is in regulation.

10.4.4 Automatic Transition into 100% Mode

Once the input voltage comes close to the output voltage, the TPS82740 stops switching and enters 100% duty cycle operation. It connects the output VOUT via the inductor and the internal high side MOSFET switch to the input VIN, once the input voltage V_IN falls below the 100% mode enter threshold, V_{TH_100-} . In 100% mode switching stops eliminating output voltage ripple. Because the output is connected to the input, the output voltage tracks the input voltage minus the voltage drop across the internal high side switch and the inductor caused by the output current. Once the input voltage increases and trips the 100% mode exit threshold, V_{TH_100+} , the TPS82740 turns on and starts switching again. See Figure 40, Figure 18, Figure 19 and Figure 20.

Figure 40. Automatic Transition into 100% Mode