Once the voltage at CS_ILIM exceeds 1.05 V, the device will execute cycle-by-cycle current limiting. The controller output is turned on at the beginning of each cycle until such point that CS_ILIM voltage reaches the current sense threshold V_{CS_ILIM}, when the output is turned off. At the same time, each time the voltage at CS_ILIM reaches 1.05 V, the capacitor at C_HICC is charged via a 80-μA current (hiccup delay current). This hiccup delay current is terminated at the end of the clock cycle. As long as there is still an overcurrent being detected, the cycle-by-cycle limiting will continue until the voltage on C_HICC reaches 0.6 V. This cycle-by-cycle limiting period is referred to as the delay mode. As such, the capacitor C_HICC can be chosen to dictate the amount of time that the controller will spend in delay mode.

Equation 13.

Note that this equation is an approximation since:

• depending on the system behavior and if C_HICC has been charged previously, C_HICC may not start at 0 V as assumed by the equation
• the 80-μA charging current is a pulsed current, the duration of which will be dictated by the nature of the overcurrent (that is,. when the current sense threshold is reached during each clock cycle)

After the voltage on HICC pin reaches 0.6 V, the SS pin of the controller is discharged and switching stops. The voltage on HICC is then quickly pulled up to 1 V with the pull-up current limited to approximately 1 mA. Once HICC voltage reaches 1 V, the 1-μA hiccup restart current begins to discharge C_HICC. The controller will not switch until HICC voltage falls to 0.3 V. Once the voltage falls to 0.3 V, the controller will initiate its soft-start sequence again. If the overcurrent has disappeared, normal operation will resume. The hiccup time, which is the entire non-switching period, can be calculated using Equation 14.

Equation 14.

In summary, the capacitor C_HICC on the HICC pin controls the amount of time the controller spends performing cycle-by-cycle limiting before switching stops, and also controls the amount of time switching is disabled before re-start is attempted again. It is recommended to use a minimum of 3.3 nF for C_HICC. Figure 8-15 shows the typical behavior during hiccup mode. Note that the OUTB and corresponding CS_ILIM waveforms are only applicable for TPS7H5001-SP and TPS7H5004-SP.

Figure 8-15 Cycle-by-Cycle Current Limit Delay Timer and Hiccup Restart Timer