ZHCSMP6A November 2020 – December 2021 TPS7H4010-SEP
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Synchronous Step-Down Regulator
- 7.3.2 Auto Mode and FPWM Mode
- 7.3.3 Fixed-Frequency Peak Current-Mode Control
- 7.3.4 Adjustable Output Voltage
- 7.3.5 Enable and UVLO
- 7.3.6 Internal LDO, VCC_UVLO, and BIAS Input
- 7.3.7 Soft Start and Voltage Tracking
- 7.3.8 Adjustable Switching Frequency
- 7.3.9 Frequency Synchronization and Mode Setting
- 7.3.10 Internal Compensation and CFF
- 7.3.11 Bootstrap Capacitor and VBOOT-UVLO
- 7.3.12 Power-Good and Overvoltage Protection
- 7.3.13 Overcurrent and Short-Circuit Protection
- 7.3.14 Thermal Shutdown
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Output Voltage Setpoint
- 8.2.2.2 Switching Frequency
- 8.2.2.3 Input Capacitors
- 8.2.2.4 Inductor Selection
- 8.2.2.5 Output Capacitor Selection
- 8.2.2.6 Feed-Forward Capacitor
- 8.2.2.7 Bootstrap Capacitors
- 8.2.2.8 VCC Capacitor
- 8.2.2.9 BIAS
- 8.2.2.10 Soft Start
- 8.2.2.11 Undervoltage Lockout Setpoint
- 8.2.2.12 PGOOD
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機械數(shù)據(jù) (封裝 | 引腳)
- RNP|30
- KGD|0
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RNP|30
訂購信息
7.3.5 Enable and UVLO
The TPS7H4010-SEP regulates output voltage when the VCC voltage is higher than the undervoltage lock out (UVLO) level, VCC_UVLO, and the EN voltage is higher than VEN_VOUT_H.
The internal LDO output voltage VCC is turned on when the EN voltage is higher than VEN_VCC_H. The precision enable circuitry is also turned on when VCC is above UVLO. Normal operation of the TPS7H4010-SEP with regulated output voltage is enabled when the EN voltage is greater than VEN_VOUT_H. When the EN voltage is less than VEN_VCC_L, the device is in shutdown mode. The internal dividers make sure VEN_VOUT_H is always higher than VEN_VCC_H.
The EN pin cannot be left floating. The simplest way to enable the operation of the TPS7H4010-SEP is to connect the EN pin to PVIN, which allows self-start-up of the TPS7H4010-SEP when VIN rises. Use of a pullup resistor between PVIN and EN pins helps reduce noise coupling from PVIN pin to the EN pin.
Many applications benefit from employing an enable divider to establish a customized system UVLO. This can be used either for sequencing, system timing requirement, or to reduce the occurrence of deep discharge of a battery power source. Figure 7-5 shows how to use a resistor divider to set a system UVLO level. An external logic output can also be used to drive the EN pin for system sequencing.
Figure 7-5 System UVLOWith a selected RENT, the RENB can be calculated by Equation 10:
where
- VIN_ON_H is the desired supply voltage threshold to turn on this device
Note that the divider adds to supply quiescent current by VIN / (RENT + RENB). Small RENT and RENB values add more quiescent current loss. However, large divider values make the node more sensitive to noise. RENT in the hundreds of kΩ range is a good starting point.