ZHCSMP6A November 2020 – December 2021 TPS7H4010-SEP
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Synchronous Step-Down Regulator
- 7.3.2 Auto Mode and FPWM Mode
- 7.3.3 Fixed-Frequency Peak Current-Mode Control
- 7.3.4 Adjustable Output Voltage
- 7.3.5 Enable and UVLO
- 7.3.6 Internal LDO, VCC_UVLO, and BIAS Input
- 7.3.7 Soft Start and Voltage Tracking
- 7.3.8 Adjustable Switching Frequency
- 7.3.9 Frequency Synchronization and Mode Setting
- 7.3.10 Internal Compensation and CFF
- 7.3.11 Bootstrap Capacitor and VBOOT-UVLO
- 7.3.12 Power-Good and Overvoltage Protection
- 7.3.13 Overcurrent and Short-Circuit Protection
- 7.3.14 Thermal Shutdown
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Output Voltage Setpoint
- 8.2.2.2 Switching Frequency
- 8.2.2.3 Input Capacitors
- 8.2.2.4 Inductor Selection
- 8.2.2.5 Output Capacitor Selection
- 8.2.2.6 Feed-Forward Capacitor
- 8.2.2.7 Bootstrap Capacitors
- 8.2.2.8 VCC Capacitor
- 8.2.2.9 BIAS
- 8.2.2.10 Soft Start
- 8.2.2.11 Undervoltage Lockout Setpoint
- 8.2.2.12 PGOOD
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
請參考 PDF 數據表獲取器件具體的封裝圖。
機械數據 (封裝 | 引腳)
- RNP|30
- KGD|0
散熱焊盤機械數據 (封裝 | 引腳)
- RNP|30
訂購信息
7.3.9 Frequency Synchronization and Mode Setting
The TPS7H4010-SEP switching action can synchronize to an external clock from 350 kHz to 2.2 MHz. TI recommends connecting the external clock to the SYNC/MODE pin with an appropriate termination resistor. Ground the SYNC/MODE pin if not used.
Figure 7-13 Frequency SynchronizationRecommendations for the external clock include a high level no lower than 2 V, low level no higher than 0.4 V, duty cycle between 10% and 90%, and both positive and negative pulse width no shorter than 80 ns. When the external clock fails at logic high or low, the TPS7H4010-SEP switches at the frequency programmed by the RT resistor after a time-out period. TI recommends connecting a resistor to the RT pin such that the internal oscillator frequency is the same as the external clock frequency. This allows the regulator to continue operating at approximately the same switching frequency if the external clock fails with the same control loop behavior.
The SYNC/MODE pin is also used as an operation mode control input.
- To set the operation in auto mode, connect SYNC/MODE pin to ground, or a logic signal lower than 0.3 V.
- To set the operation in FPWM mode, connect SYNC/MODE pin to a bias voltage or logic signal greater than 0.6 V.
- When the TPS7H4010-SEP is synchronized to an external clock, the operation mode is FPWM.
| SYNC/MODE INPUT | SWITCHING FREQUENCY | OPERATING MODE | LIGHT LOAD BEHAVIOR |
|---|---|---|---|
| Logic low | Set by RT resistor | Auto mode |
|
| Logic high | Set by RT resistor | FPWM mode |
|
| External clock | Set by external clock |