ZHCSPL6 January 2022 TPS7H4003-SEP
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 VIN and Power VIN Pins (VIN and PVIN)
- 7.3.2 Voltage Reference
- 7.3.3 Adjusting the Output Voltage
- 7.3.4 Safe Start-Up Into Prebiased Outputs
- 7.3.5 Error Amplifier
- 7.3.6 Enable and Adjust UVLO
- 7.3.7 Adjustable Switching Frequency and Synchronization (SYNC)
- 7.3.8 Soft-Start (SS/TR)
- 7.3.9 Power Good (PWRGD)
- 7.3.10 Sequencing
- 7.3.11 Output Overvoltage Protection (OVP)
- 7.3.12 Overcurrent Protection
- 7.3.13 Thermal Shutdown
- 7.3.14 Turn-On Behavior
- 7.3.15 Slope Compensation
- 7.3.16 Small Signal Model for Frequency Compensation
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Operating Frequency
- 8.2.2.2 Output Inductor Selection
- 8.2.2.3 Output Capacitor Selection
- 8.2.2.4 Output Schottky Diode
- 8.2.2.5 Input Capacitor Selection
- 8.2.2.6 Soft-Start Capacitor Selection
- 8.2.2.7 Undervoltage Lockout (UVLO) Set Point
- 8.2.2.8 Output Voltage Feedback Resistor Selection
- 8.2.2.9 Compensation Component Selection
- 8.2.3 Parallel Operation
- 8.2.4 Application Curve
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- DDW|44
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- DDW|44
訂購信息
7.3.6 Enable and Adjust UVLO
The EN pin provides electrical on and off control of the device. When the EN pin voltage exceeds the threshold voltage, the device enables operation. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low Iq state. The EN pin has an internal pullup current source, allowing the user to float the EN pin for enabling the device. If an application requires controlling the EN pin, use open-drain or open-collector output logic to interface with the pin.
The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 150-mV typical.
If an application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVIN in split-rail applications, then the EN pin can be configured as shown in Figure 7-1, Figure 7-2, and Figure 7-3. A ceramic capacitor in parallel with the bottom resistor R2 is recommended to reduce noise on the EN pin as used in the TPS7H4003-SEP evaluation module (EVM). See the TPS7H4003EVM-CVAL Evaluation Module (EVM) User's Guide for more information.
The EN pin has a small pullup current, Ip, which sets the default state of the pin to enable when no external components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO function because it increases by Ih after the EN pin crosses the enable threshold. Calculate the UVLO thresholds with Equation 2 and Equation 3.
Figure 7-1 Adjustable VIN UVLO
Figure 7-2 Adjustable PVIN UVLO
Figure 7-3 Adjustable VIN and PVIN UVLO
where
- Ih = 3 μA
- Ip = 6.1 μA
- VENRISING = 1.14 V
- VENFALLING = 1.11 V