ZHCSGF3B July 2017 – January 2019 TPS7A92
PRODUCTION DATA.
The TPS7A92 is designed and characterized for operation with ceramic capacitors of 10 µF or greater at the input and 22 µF or greater at the output. Locate the input and output capacitors as near as practical to the input and output pins to minimize the trace inductance from the capacitor to the device.
Attention must be given to the input capacitance to minimize transient input droop during startup and load current steps. Simply using very large ceramic input capacitances can cause unwanted ringing at the output if the input capacitor (in combination with the wire-lead inductance) creates a high-Q peaking effect during transients, which is why short, well-designed interconnect traces to the upstream supply are needed to minimize ringing. Damping of unwanted ringing can be accomplished by using a tantalum capacitor, with a few hundred milliohms of ESR, in parallel with the ceramic input capacitor. The UVLO circuit responds quickly to glitches on VIN and disables the output of the device if this rail starts to collapse too quickly. Use an input capacitor that is large enough to slow input transients to less then two volts per microsecond.