ZHCSEP4A January 2016 – February 2016 TPS7A85
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configurations and Functions
- 6 Specifications
- 7 Detailed Description
-
8 Application and Implementation
- 8.1
Application Information
- 8.1.1 Recommended Capacitor Types
- 8.1.2 Input and Output Capacitor Requirements (CIN and COUT)
- 8.1.3 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
- 8.1.4 Feed-Forward Capacitor (CFF)
- 8.1.5 Soft-Start and In-Rush Current
- 8.1.6 Optimizing Noise and PSRR
- 8.1.7 ANY-OUT Programmable Output Voltage
- 8.1.8 ANY-OUT Operation
- 8.1.9 Increasing ANY-OUT Resolution for LILO Conditions
- 8.1.10 Current Sharing
- 8.1.11 Adjustable Operation
- 8.1.12 Sequencing Requirements
- 8.1.13 Power-Good (PG) Operation
- 8.1.14 Undervoltage Lockout (UVLO) Operation
- 8.1.15 Dropout Voltage (VDO)
- 8.1.16 Behavior when Transitioning from Dropout into Regulation
- 8.1.17 Load Transient Response
- 8.1.18 Negatively-Biased Output
- 8.1.19 Reverse Current Protection
- 8.1.20 Power Dissipation (PD)
- 8.2 Typical Applications
- 8.1
Application Information
- 9 Power-Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
5 Pin Configurations and Functions
RGR Package
3.5-mm × 3.5-mm, 20-Pin VQFN
Top View
Pin Functions
| PIN | DESCRIPTION | ||
|---|---|---|---|
| NAME | NO. | I/O | |
| 50mV | 5 | I | ANY-OUT voltage setting pins. Connect these pins to ground, SNS, or leave floating. Connecting these pins to ground increases the output voltage, whereas connecting these pins to SNS increases the resolution of the ANY-OUT network but decreases the range of the network; multiple pins can be simultaneously connected to GND or SNS to select the desired output voltage. Leave these pins floating (open) when not in use. See the ANY-OUT Programmable Output Voltage section for additional details. |
| 100mV | 6 | ||
| 200mV | 7 | ||
| 400mV | 9 | ||
| 800mV | 10 | ||
| 1.6V | 11 | ||
| BIAS | 12 | I | BIAS supply voltage. This pin enables the use of low-input voltage, low-output (LILO) voltage conditions (that is, VIN = 1.2 V, VOUT = 1 V) to reduce power dissipation across the die. The use of a BIAS voltage improves dc and ac performance for VIN ≤ 2.2 V. A 10-µF capacitor or larger must be connected between this pin and ground. If not used, this pin must be left floating or tied to ground. |
| EN | 14 | I | Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low disables the device. If enable functionality is not required, this pin must be connected to IN. If enable functionality is required, VEN must always be high after VIN is established when a BIAS supply is used. See the Sequencing Requirements section for more details. |
| FB | 3 | I | Feedback pin connected to the error amplifier. Although not required, a 10-nF feed-forward capacitor from FB to OUT (as close to the device as possible) is recommended to maximize ac performance. The use of a feed-forward capacitor can disrupt PG (power good) functionality. See the ANY-OUT Programmable Output Voltage and Adjustable Operation sections for more details. |
| GND | 8, 18 | — | Ground pin. These pins must be connected to ground, the thermal pad, and each other with a low-impedance connection. |
| IN | 15-17 | I | Input supply voltage pins. A 47-μF or larger ceramic capacitor (25 μF or greater of effective capacitance) from IN to ground is recommended to reduce the impedance of the input supply. Place the input capacitor as close to the input as possible. See the Input and Output Capacitor Requirements section for more details. |
| NR/SS | 13 | — | Noise-reduction and soft-start pin. Connecting an external capacitor between this pin and ground reduces reference voltage noise and also enables the soft-start function. Although not required, a 10-nF or larger capacitor is recommended to be connected from NR/SS to GND (as close to the pin as possible) to maximize ac performance. See the Noise-Reduction and Soft-Start Capacitor section for more details. |
| OUT | 1, 19, 20 | O | Regulated output pins. A 47-μF or larger ceramic capacitor (25 μF or greater of effective capacitance) from OUT to ground is required for stability and must be placed as close to the output as possible. Minimize the impedance from the OUT pin to the load. See the Input and Output Capacitor Requirements section for more details. |
| PG | 4 | O | Active-high, power-good pin. An open-drain output indicates when the output voltage reaches 89.3% of the target. The use of a feed-forward capacitor can disrupt PG (power good) functionality. See the Power-Good (PG) Function section for more details. |
| SNS | 2 | I | Output voltage sense input pin. This pin connects the internal R1 resistor to the output. Connect this pin to the load side of the output trace only if the ANY-OUT feature is used. If the ANY-OUT feature is not used, leave this pin floating. See the ANY-OUT Programmable Output Voltage and Adjustable Operation sections for more details. |
| Thermal pad | — | Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND. | |