ZHCSEI2B January 2016 – June 2021 TPS7A84
PRODUCTION DATA
At 3.0 A, the dropout of the TPS7A84 has 180-mV maximum dropout over temperature, thus a 400-mV headroom is sufficient for operation over both input and output voltage accuracy. The bias rail is provided for better performance for the LILO conditions. The PSRR is greater than 40 dB in these conditions, as per the Figure 6-1 curve. Noise is less than 10 μVRMS, as per the Figure 6-8 curve.
The ANY-OUT internal resistor network is also used for maximum accuracy.
To achieve 0.9 V on the output, the 100mV pin is grounded. The voltage value of 100 mV is added to the 0.8-V internal reference voltage for VOUT(nom) equal to 0.9 V, as described in Equation 13.
Input and output capacitors are selected in accordance with the Section 8.1.1 section. Ceramic capacitances of 47 μF for the input and one 47-μF capacitor in parallel with two 10-μF capacitors for the output are selected.
To satisfy the required start-up time and still maintain low-noise performance, a 100-nF CNR/SS is selected. This value is calculated with Equation 14.
At the 3.0-A maximum load, the internal power dissipation is 1.2 W and corresponds to a 42.48°C junction temperature rise for the RGR package on a standard JEDEC board. With an 55°C maximum ambient temperature, the junction temperature is at 97.5°C. To further minimize noise, a feed-forward capacitance (CFF) of 10 nF is selected.