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ZHCSO39B May 2022 – August 2022 TPS7A74

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

DSD|8
- MPDS238B

散熱焊盤機械數據 (封裝 | 引腳)

DSD|8
- QFND348B

訂購信息

6.5 Electrical Characteristics

at V_EN = 1.1 V, V_IN = V_OUT + 0.3 V, C_BIAS = 0.1 μF, C_IN = C_OUT = 10 μF, C_NR = 10 nF, I_OUT = 10 mA, V_BIAS = 5.0 V (3), and T_J = –40°C to 125°C (unless otherwise noted); typical values are at T_J = 25°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_REF	Internal reference (adj.)		0.641	0.65	0.659	V
	Output accuracy (1)(5)(6)	2.97 V ≤ V_BIAS ≤ 6 V, 0 mA ≤ I_OUT ≤ 1.5 A	–1.5	±0.5	1.5	%
	Line regulation (V_BIAS)	Max(2.7 V, V_OUT + 1.6 V) ≤ V_BIAS ≤ 6 V		0.2	0.32	%/V
	Line regulation (V_IN)	V_OUT(nom) + 0.15 V ≤ V_IN ≤ 6 V		0.01	0.05	%/V
	Load regulation	0 mA ≤ I_OUT ≤ 1.5 A		0.33		%/A
V_DO(IN)	V_IN dropout voltage⁽²⁾	I_OUT = 1.5 A, V_BIAS – V_OUT(nom) ≥ 2.8 V		150	180	mV
V_DO(BIAS)	V_BIAS dropout voltage⁽²⁾	I_OUT = 1.5 A, V_IN = V_BIAS		1.1	1.3	V
I_CL	Output current limit	V_OUT = 80% × V_OUT(nom)	2	2.7	3.3	A
I_BIAS	BIAS pin current	I_OUT = 10 mA		0.25	0.33	mA
I_SHDN	Shutdown supply current (I_GND)	V_EN ≤ 0.4 V, V_IN = 6 V, V_BIAS = 6 V		1	55	μA
I_FB	Feedback pin current		–1	0.15	1	μA
V_BIAS(UVLO)	Bias rail UVLO rising threshold		1.04	1.4	1.65	V
V_{BIAS(UVLO), HYST}	Bias rail UVLO hysteresis		0.02	0.06	0.07	V
V_{IN(UVLO), rising}	In rail UVLO rising threshold		0.39	0.455	0.5	V
V_{IN(UVLO), falling}	In rail UVLO falling threshold		0.21	0.26	0.3	V
t_STR	Minimum start-up time	R_LOAD for I_OUT = 1.0 A, C_SS = open	35		335	μs
I_SS	Soft-start charging current	V_SS = 0 V	8	17	31	μA
V_SS	Soft-start pin disable voltage	V_EN = 0 V		0	50	mV
PSRR	Power-supply rejection (V_BIAS to V_OUT)	1 kHz, Iout = 1.5 A, Vin = 1.8 V, Vout = 1.5 V		57		dB
PSRR	Power-supply rejection (V_BIAS to V_OUT)	300 kHz, Iout = 1.5 A, Vin = 1.8 V, Vout = 1.5 V		27		dB
PSRR	Power-supply rejection (V_IN to V_OUT)	BW = 10 Hz to 1 MHz, I_OUT = 1 A, V_IN = 2.05 V, V_OUT = 1.8 V		27		dB
Vn	Output voltage noise	BW = 10 Hz to 100 kHz, I_OUT = 1 A, V_IN = 0.95 V, V_OUT = 0.65 V		7.1		μV_RMS
V_EN(hi)	Enable input high level		1.1		5.5	V
V_EN(lo)	Enable input low level		0		0.4	V
V_EN(hys)	Enable pin hysteresis			55		mV
V_EN(dg)	Enable pin deglitch time			20		μs
I_EN	Enable pin current	V_EN = 5 V		0.1	0.2	μA
R_{PULLDOWN(OUT)}	V_BIAS = 5 V, V_EN = 0 V			0.6	1	k?
R_PULLDOWN(FB)	V_BIAS = 5 V, V_EN = 0 V			120		?
T_SD	Thermal shutdown temperature	Shutdown, temperature increasing		165		℃
T_SD	Thermal shutdown temperature	Reset, temperature decreasing		140		℃

(1) Adjustable devices tested at 0.65 V; resistor tolerance is not taken into account.

(2) Dropout is defined as the voltage from V_IN to V_OUT when V_OUT is 3% below nominal.

(3) V_BIAS = V_{DO_MAX(BIAS)} + V_OUT for V_OUT ≥ 3.4 V

(4) The device is not tested under conditions where V_IN > V_OUT + 1.65 V and I_OUT = 1.5 A, because the power dissipation is higher than the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the power dissipation limit of the package under test.

(5) The device is not tested under conditions where V_IN > V_OUT + 1.65 V and I_OUT = 1.5 A, because the power dissipation is higher than the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the power dissipation limit of the package under test.