ZHCSRX9A August 2023 – January 2024 TPS7A53B
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Detailed Description
-
7 Application and Implementation
- 7.1
Application Information
- 7.1.1 Recommended Capacitor Types
- 7.1.2 Soft-Start and Inrush Current
- 7.1.3 Optimizing Noise and PSRR
- 7.1.4 Charge Pump Noise
- 7.1.5 Current Sharing
- 7.1.6 Adjustable Operation
- 7.1.7 Power-Good Operation
- 7.1.8 Undervoltage Lockout (UVLO) Operation
- 7.1.9 Dropout Voltage (VDO)
- 7.1.10 Device Behavior During Transition From Dropout Into Regulation
- 7.1.11 Load Transient Response
- 7.1.12 Reverse Current Protection Considerations
- 7.1.13 Power Dissipation (PD)
- 7.1.14 Estimating Junction Temperature
- 7.1.15 TPS7A53EVM Thermal Analysis
- 7.2 Typical Application
- 7.3 Power Supply Recommendations
- 7.4 Layout
- 7.1
Application Information
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RPS|12
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購信息
6.3.2.3 Power-Good Output (PG)
The PG signal provides an easy solution to meet demanding sequencing requirements because PG signals when the output nears the nominal value. PG can be used to signal other devices in a system when the output voltage is near, at, or above the set output voltage (VOUT(nom)). Figure 6-4 shows a simplified schematic.
The PG signal is an open-drain digital output that requires a pullup resistor to a voltage source and is active high. The PG circuit sets the PG pin into a high-impedance state to indicate that the power is good.
Using a large feed-forward capacitor (CFF) delays the output voltage and, because the PG circuit monitors the FB pin, the PG signal can indicate a false positive.
Figure 6-4 Simplified PG Circuit