ZHCSRX9A August 2023 – January 2024 TPS7A53B
PRODUCTION DATA
The RPS package is a 2.2mm × 2.5mm, 12-pin VQFN with 25μm plating on each via. The EVM is a 3 inch by 3 inch (7.62 mm × 7.62 mm) PCB comprised of four layers. Table 7-3 lists an overview of the EVM stackup. Figure 7-5 to Figure 7-9 provide layer details for the EVM.
| LAYER | NAME | MATERIAL | THICKNESS (mil) |
|---|---|---|---|
| 1 | Top overlay | — | — |
| 2 | Top solder | Solder resist | 0.40 |
| 3 | Top layer | Copper | 1.40 |
| 4 | Dielectric 1 | FR-4, high TG | 18.50 |
| 5 | Mid layer 1 | Copper | 1.40 |
| 6 | Dielectric 2 | FR-4, high TG | 18.60 |
| 7 | Mid layer 2 | Copper | 1.40 |
| 8 | Dielectric 3 | FR-4, high TG | 18.50 |
| 9 | Bottom layer | Copper | 1.40 |
| 10 | Bottom solder | Solder resist | 0.40 |
Figure 7-10 shows the thermal gradient on the PCB that results when using a 1W power dissipation through the pass transistor with a 25°C ambient temperature.
Figure 7-10 PCB Thermal GradientFor additional information on the PCB, see the TPS7A53EVM-031 Evaluation Module user guide.