The TPS7A53B features a programmable, monotonic, voltage-controlled soft-start that is set with an external capacitor (C_NR/SS). Use an external C_NR/SS to minimize inrush current into the output capacitors. This soft-start feature eliminates power-up initialization problems when powering field-programmable gate arrays (FPGAs), digital signal processors (DSPs), or other processors. The controlled voltage ramp of the output also reduces peak inrush current during start-up, minimizing start-up transients to the input power bus.

To achieve a monotonic start-up, the TPS7A53B error amplifier tracks the voltage ramp of the external soft-start capacitor until the voltage approaches the internal reference. The soft-start ramp time depends on the soft-start charging current (I_NR/SS), the soft-start capacitance (C_NR/SS), and the internal reference (V_NR/SS). Use Equation 1 to calculate the soft-start ramp time:

I_NR/SS is provided in the Electrical Characteristics table and has a typical value of 6.2μA.

The noise-reduction capacitor, in conjunction with the noise-reduction resistor, forms a low-pass filter (LPF) that filters out noise from the reference before being gained up with the error amplifier, thereby reducing the device noise floor. The LPF is a single-pole filter and Equation 2 calculates the cutoff frequency. The typical value of R_NR is 250kΩ. Increasing the C_NR/SS capacitor has a greater affect because the output voltage increases when the noise from the reference is gained up even more at higher output voltages. For low-noise applications, use a 10nF to 1μF C_NR/SS.