ZHCSLY5A August 2020 – July 2021 TPS65994AD
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| I2C_EC_IRQ , I2C2s_IRQ | ||||||
| OD_VOL_IRQ | Low level output voltage | IOL = 2 mA | 0.4 | V | ||
| OD_LKG_IRQ | Leakage Current | Output is Hi-Z, VI2Cx_IRQ = 3.45 V | –1 | 1 | μA | |
| I2C3m_IRQ | ||||||
| IRQ_VIH | High-Level input voltage | VLDO_3V3 = 3.3V | 1.3 | V | ||
| IRQ_VIH_THRESH | High-Level input voltage threshold | VLDO_3V3 = 3.3V | 0.72 | 1.3 | V | |
| IRQ_VIL | low-level input voltage | VLDO_3V3 = 3.3V | 0.54 | V | ||
| IRQ_VIL_THRESH | low-level input voltage threshold | VLDO_3V3 = 3.3V | 0.54 | 1.08 | V | |
| IRQ_HYS | input hysteresis voltage | VLDO_3V3 = 3.3V | 0.09 | V | ||
| IRQ_DEG | input deglitch | 20 | ns | |||
| IRQ_ILKG | I2C3m_IRQ leakage current | VI2C3m_IRQ = 3.45 V | –1 | 1 | μA | |
| SDA and SCL Common Characteristics (Master, Slave) | ||||||
| VIL | Input low signal | VLDO_3V3=3.3V, | 0.54 | V | ||
| VIH | Input high signal | VLDO_3V3=3.3V, | 1.3 | V | ||
| VHYS | Input hysteresis | VLDO_3V3=3.3V | 0.165 | V | ||
| VOL | Output low voltage | IOL=3 mA | 0.36 | V | ||
| ILEAK | Input leakage current | Voltage on pin = VLDO_3V3 | –3 | 3 | μA | |
| IOL | Max output low current | VOL=0.4 V | 15 | mA | ||
| IOL | Max output low current | VOL=0.6 V | 20 | mA | ||
| tf | Fall time from 0.7*VDD to 0.3*VDD | VDD = 1.8V, 10 pF ≤ Cb ≤ 400 pF | 12 | 80 | ns | |
| VDD = 3.3V, 10 pF ≤ Cb ≤ 400 pF | 12 | 150 | ns | |||
| tSP | I2C pulse width surpressed | 50 | ns | |||
| CI | pin capacitance (internal) | 10 | pF | |||
| Cb | Capacitive load for each bus line (external) | 400 | pF | |||
| tHD;DAT | Serial data hold time | VDD = 1.8V or 3.3V | 0 | ns | ||
| SDA and SCL Standard Mode Characteristics (Slave) | ||||||
| fSCLS | Clock frequency | VDD = 1.8V or 3.3V | 100 | kHz | ||
| tVD;DAT | Valid data time | Transmitting Data, VDD = 1.8V or 3.3V, SCL low to SDA output valid | 3.45 | μs | ||
| tVD;ACK | Valid data time of ACK condition | Transmitting Data, VDD = 1.8V or 3.3V, ACK signal from SCL low to SDA (out) low | 3.45 | μs | ||
| SDA and SCL Fast Mode Characteristics (Slave) | ||||||
| fSCLS | Clock frequency | VDD = 1.8V or 3.3V | 100 | 400 | kHz | |
| tVD;DAT | Valid data time | Transmitting data, VDD = 1.8V, SCL low to SDA output valid | 0.9 | μs | ||
| tVD;ACK | Valid data time of ACK condition | Transmitting data, VDD = 1.8V or 3.3V, ACK signal from SCL low to SDA (out) low | 0.9 | μs | ||
| SDA and SCL Fast Mode Plus Characteristics (Slave) | ||||||
| fSCLS | Clock frequency (1) | VDD = 1.8V or 3.3V, master controls SCL frequency such that: tLOW > tVD;ACK + tSU;DAT, TJ ≤ 65oC | 400 | 1000 | kHz | |
| tVD;DAT | Valid data time | Transmitting data, VDD = 1.8V or 3.3V, SCL low to SDA output valid, TJ ≤ 65 oC | 0.55 | μs | ||
| tVD;ACK | Valid data time of ACK condition | Transmitting data, VDD = 1.8V or 3.3V, ACK signal from SCL low to SDA (out) low, TJ ≤ 65 oC | 0.55 | μs | ||
| SDA and SCL Fast Mode Characteristics (Master) | ||||||
| fSCLM | Clock frequency for master(3) | VDD = 3.3V(4) | 400 | 410 | kHz | |
| VDD = 1.8V | 390 | 400 | ||||
| tHD;STA | Start or repeated start condition hold time |
VDD = 3.3V | 0.6 | μs | ||
| tLOW | Clock low time | VDD = 3.3V | 1.3 | μs | ||
| tHIGH | Clock high time | VDD = 3.3V | 0.6 | μs | ||
| tSU;STA | Start or repeated start condition setup time |
VDD = 3.3V | 0.6 | μs | ||
| tSU;DAT | Serial data setup time | Transmitting data, VDD = 3.3V | 100 | ns | ||
| tSU;STO | Stop condition setup time | VDD = 3.3V | 0.6 | μs | ||
| tBUF | Bus free time between stop and start |
VDD = 3.3V | 1.3 | μs | ||
| tVD;DAT | Valid data time | Transmitting data, VDD = 3.3V, SCL low to SDA output valid | 0.9 | μs | ||
| tVD;ACK | Valid data time of ACK condition | Transmitting data, VDD = 3.3V, ACK signal from SCL low to SDA (out) low | 0.9 | μs | ||