ZHCSLY5A August 2020 – July 2021 TPS65994AD
PRODUCTION DATA
The TPS65994AD has two I2C slave interface ports: I2C_EC and I2C2s. I2C port I2C_EC is comprised of the I2C_EC_SDA, I2C_EC_SCL, and I2C_EC_IRQ pins. I2C I2C2s is comprised of the I2C2s_SDA, I2C2s_SCL, and I2C2s_IRQ pins. These interfaces provide general status information about the TPS65994AD, as well as the ability to control the TPS65994AD behavior, supporting communications to/from a connected device and/or cable supporting BMC USB-PD, and providing information about connections detected at the USB-C receptacle.
When the TPS65994AD is in 'APP ' mode it is recommended to use Standard Mode or Fast Mode (that is a clock speed no higher than 400 kHz). However, in the 'BOOT' mode when a patch bundle is loaded Fast Mode Plus may be used (see fSCLS).
The TPS65994AD has one I2C master interface port: I2C3m. I2C3m is comprised of the I2C3m_SDA, I2C3m_SCL, and I2C3m_IRQ1 pins. This interface can be used to read from or write to external slave devices. During boot the TPS65994AD attempts to read patch and Application Configuration data from an external EEPROM with a 7-bit slave address of 0x50. The EEPROM should be at least kilo-bytes.
| I2C Bus | Type | Typical Usage |
|---|---|---|
| I2C_EC | Slave | Connect to an Embedded Controller (EC). Used to load the patch and application configuration. |
| I2C2s | Slave | Connect to a TBT controller or second master. |
| I2C3m | Master | Connect to a TBT retimer, USB Type-C mux, I2C EEPROM, or other slave. Use the LDO_3V3 pin as the pull-up voltage. Multi-master configuration is not supported. |