ZHCSDM4D december 2014 – may 2023 TPS65263-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Adjusting the Output Voltage
- 7.3.2 Enable and Adjusting UVLO
- 7.3.3 Soft-Start Time
- 7.3.4 Power-Up Sequencing
- 7.3.5 V7V Low-Dropout Regulator and Bootstrap
- 7.3.6 Out-of-Phase Operation
- 7.3.7 Output Overvoltage Protection (OVP)
- 7.3.8 PSM
- 7.3.9 Slope Compensation
- 7.3.10 Overcurrent Protection
- 7.3.11 Power Good
- 7.3.12 Thermal Shutdown
- 7.4 Device Functional Modes
- 7.5 Register Maps
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Mechanical, Packaging, and Orderable Information
8.2 Typical Application
The following design procedure can be used to select component values for the TPS65263-Q1. This section presents a simplified discussion of the design process.
Figure 8-1 Typical
Application Schematic