ZHCSH55B December   2017  – September 2018 TPS65218D0

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

1. 1 器件概述
   1. 1.1 特性
   2. 1.2 應(yīng)用
   3. 1.3 說明
   4. 1.4 簡化原理圖
2. 2 修訂歷史記錄
3. 3 Pin Configuration and Functions
   1. 3.1 Pin Functions
      1.      Pin Functions
4. 4 Specifications
   1. 4.1 Absolute Maximum Ratings
   2. 4.2 ESD Ratings
   3. 4.3 Recommended Operating Conditions
   4. 4.4 Thermal Information
   5. 4.5 Electrical Characteristics
   6. 4.6 Timing Requirements
   7. 4.7 Typical Characteristics
5. 5 Detailed Description
   1. 5.1 Overview
   2. 5.2 Functional Block Diagram
   3. 5.3 Feature Description
      1. 5.3.1 Wake-Up and Power-Up and Power-Down Sequencing
         1. 5.3.1.1  Power-Up Sequencing
         2. 5.3.1.2  Power-Down Sequencing
         3. 5.3.1.3  Strobes 1 and 2
         4. 5.3.1.4  Supply Voltage Supervisor and Power Good (PGOOD)
         5. 5.3.1.5  Backup Supply Power-Good (PGOOD_BU)
         6. 5.3.1.6  Internal LDO (INT_LDO)
         7. 5.3.1.7  Current Limited Load Switches
            1. 5.3.1.7.1 Load Switch 1 (LS1)
            2. 5.3.1.7.2 Load Switch 2 (LS2)
            3. 5.3.1.7.3 Load Switch 3 (LS3)
         8. 5.3.1.8  LDO1
         9. 5.3.1.9  Coin Cell Battery Voltage Acquisition
         10. 5.3.1.10 UVLO
         11. 5.3.1.11 Power-Fail Comparator
         12. 5.3.1.12 Battery-Backup Supply Power-Path
         13. 5.3.1.13 DCDC3 / DCDC4 Power-Up Default Selection
         14. 5.3.1.14 I/O Configuration
             1. 5.3.1.14.1 Configuring GPO2 as Open-Drain Output
             2. 5.3.1.14.2 Using GPIO3 as Reset Signal to DCDC1 and DCDC2
         15. 5.3.1.15 Push Button Input (PB)
             1. 5.3.1.15.1 Signaling PB-Low Event on the nWAKEUP Pin
             2. 5.3.1.15.2 Push Button Reset
         16. 5.3.1.16 AC_DET Input (AC_DET)
         17. 5.3.1.17 Interrupt Pin (INT)
         18. 5.3.1.18 I2C Bus Operation
   4. 5.4 Device Functional Modes
      1. 5.4.1 Modes of Operation
      2. 5.4.2 OFF
      3. 5.4.3 ACTIVE
      4. 5.4.4 SUSPEND
      5. 5.4.5 RESET
   5. 5.5 Programming
      1. 5.5.1 Programming Power-Up Default Values
   6. 5.6 Register Maps
      1. 5.6.1 Password Protection
      2. 5.6.2 Freshness Seal (FSEAL) Bit
      3. 5.6.3 FLAG Register
      4. 5.6.4 TPS65218D0 Registers
         1. 5.6.4.1  CHIPID Register (subaddress = 0x0) [reset = 0x5]
            1. Table 5-8 CHIPID Register Field Descriptions
         2. 5.6.4.2  INT1 Register (subaddress = 0x1) [reset = 0x0]
            1. Table 5-9 INT1 Register Field Descriptions
         3. 5.6.4.3  INT2 Register (subaddress = 0x2) [reset = 0x0]
            1. Table 5-10 INT2 Register Field Descriptions
         4. 5.6.4.4  INT_MASK1 Register (subaddress = 0x3) [reset = 0x0]
            1. Table 5-11 INT_MASK1 Register Field Descriptions
         5. 5.6.4.5  INT_MASK2 Register (subaddress = 0x4) [reset = 0x0]
            1. Table 5-12 INT_MASK2 Register Field Descriptions
         6. 5.6.4.6  STATUS Register (subaddress = 0x5) [reset = 00XXXXXXb]
            1. Table 5-13 STATUS Register Field Descriptions
         7. 5.6.4.7  CONTROL Register (subaddress = 0x6) [reset = 0x0]
            1. Table 5-14 CONTROL Register Field Descriptions
         8. 5.6.4.8  FLAG Register (subaddress = 0x7) [reset = 0x0]
            1. Table 5-15 FLAG Register Field Descriptions
         9. 5.6.4.9  PASSWORD Register (subaddress = 0x10) [reset = 0x0]
            1. Table 5-16 PASSWORD Register Field Descriptions
         10. 5.6.4.10 ENABLE1 Register (subaddress = 0x11) [reset = 0x0]
             1. Table 5-17 ENABLE1 Register Field Descriptions
         11. 5.6.4.11 ENABLE2 Register (subaddress = 0x12) [reset = 0x0]
             1. Table 5-18 ENABLE2 Register Field Descriptions
         12. 5.6.4.12 CONFIG1 Register (subaddress = 0x13) [reset = 0x4C]
             1. Table 5-19 CONFIG1 Register Field Descriptions
         13. 5.6.4.13 CONFIG2 Register (subaddress = 0x14) [reset = 0xC0]
             1. Table 5-20 CONFIG2 Register Field Descriptions
         14. 5.6.4.14 CONFIG3 Register (subaddress = 0x15) [reset = 0x0]
             1. Table 5-21 CONFIG3 Register Field Descriptions
         15. 5.6.4.15 DCDC1 Register (offset = 0x16) [reset = 0x99]
             1. Table 5-22 DCDC1 Register Field Descriptions
         16. 5.6.4.16 DCDC2 Register (subaddress = 0x17) [reset = 0x99]
             1. Table 5-23 DCDC2 Register Field Descriptions
         17. 5.6.4.17 DCDC3 Register (subaddress = 0x18) [reset = 0x8C]
             1. Table 5-24 DCDC3 Register Field Descriptions
         18. 5.6.4.18 DCDC4 Register (subaddress = 0x19) [reset = 0xB2]
             1. Table 5-25 DCDC4 Register Field Descriptions
         19. 5.6.4.19 SLEW Register (subaddress = 0x1A) [reset = 0x6]
             1. Table 5-26 SLEW Register Field Descriptions
         20. 5.6.4.20 LDO1 Register (subaddress = 0x1B) [reset = 0x1F]
             1. Table 5-27 LDO1 Register Field Descriptions
         21. 5.6.4.21 SEQ1 Register (subaddress = 0x20) [reset = 0x0]
             1. Table 5-28 SEQ1 Register Field Descriptions
         22. 5.6.4.22 SEQ2 Register (subaddress = 0x21) [reset = 0x0]
             1. Table 5-29 SEQ2 Register Field Descriptions
         23. 5.6.4.23 SEQ3 Register (subaddress = 0x22) [reset = 0x98]
             1. Table 5-30 SEQ3 Register Field Descriptions
         24. 5.6.4.24 SEQ4 Register (subaddress = 0x23) [reset = 0x75]
             1. Table 5-31 SEQ4 Register Field Descriptions
         25. 5.6.4.25 SEQ5 Register (subaddress = 0x24) [reset = 0x12]
             1. Table 5-32 SEQ5 Register Field Descriptions
         26. 5.6.4.26 SEQ6 Register (subaddress = 0x25) [reset = 0x63]
             1. Table 5-33 SEQ6 Register Field Descriptions
         27. 5.6.4.27 SEQ7 Register (subaddress = 0x26) [reset = 0x3]
             1. Table 5-34 SEQ7 Register Field Descriptions
6. 6 Application and Implementation
   1. 6.1 Application Information
      1. 6.1.1 Applications Without Backup Battery
      2. 6.1.2 Applications Without Battery Backup Supplies
   2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
         1. 6.2.2.1 Output Filter Design
         2. 6.2.2.2 Inductor Selection for Buck Converters
         3. 6.2.2.3 Output Capacitor Selection
      3. 6.2.3 Application Curves
7. 7 Power Supply Recommendations
8. 8 Layout
   1. 8.1 Layout Guidelines
   2. 8.2 Layout Example
9. 9 器件和文檔支持
   1. 9.1 器件支持
      1. 9.1.1 第三方產(chǎn)品免責(zé)聲明
   2. 9.2 文檔支持
      1. 9.2.1 相關(guān)文檔
   3. 9.3 接收文檔更新通知
   4. 9.4 社區(qū)資源
   5. 9.5 商標(biāo)
   6. 9.6 靜電放電警告
   7. 9.7 Glossary
10. 10機械、封裝和可訂購信息