ZHCSH55B December 2017 – September 2018 TPS65218D0
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
- 1 器件概述
- 2 修訂歷史記錄
- 3 Pin Configuration and Functions
- 4 Specifications
-
5 Detailed Description
- 5.1 Overview
- 5.2 Functional Block Diagram
- 5.3
Feature Description
- 5.3.1
Wake-Up and Power-Up and Power-Down Sequencing
- 5.3.1.1 Power-Up Sequencing
- 5.3.1.2 Power-Down Sequencing
- 5.3.1.3 Strobes 1 and 2
- 5.3.1.4 Supply Voltage Supervisor and Power Good (PGOOD)
- 5.3.1.5 Backup Supply Power-Good (PGOOD_BU)
- 5.3.1.6 Internal LDO (INT_LDO)
- 5.3.1.7 Current Limited Load Switches
- 5.3.1.8 LDO1
- 5.3.1.9 Coin Cell Battery Voltage Acquisition
- 5.3.1.10 UVLO
- 5.3.1.11 Power-Fail Comparator
- 5.3.1.12 Battery-Backup Supply Power-Path
- 5.3.1.13 DCDC3 / DCDC4 Power-Up Default Selection
- 5.3.1.14 I/O Configuration
- 5.3.1.15 Push Button Input (PB)
- 5.3.1.16 AC_DET Input (AC_DET)
- 5.3.1.17 Interrupt Pin (INT)
- 5.3.1.18 I2C Bus Operation
- 5.3.1
Wake-Up and Power-Up and Power-Down Sequencing
- 5.4 Device Functional Modes
- 5.5 Programming
- 5.6
Register Maps
- 5.6.1 Password Protection
- 5.6.2 Freshness Seal (FSEAL) Bit
- 5.6.3 FLAG Register
- 5.6.4
TPS65218D0 Registers
- 5.6.4.1 CHIPID Register (subaddress = 0x0) [reset = 0x5]
- 5.6.4.2 INT1 Register (subaddress = 0x1) [reset = 0x0]
- 5.6.4.3 INT2 Register (subaddress = 0x2) [reset = 0x0]
- 5.6.4.4 INT_MASK1 Register (subaddress = 0x3) [reset = 0x0]
- 5.6.4.5 INT_MASK2 Register (subaddress = 0x4) [reset = 0x0]
- 5.6.4.6 STATUS Register (subaddress = 0x5) [reset = 00XXXXXXb]
- 5.6.4.7 CONTROL Register (subaddress = 0x6) [reset = 0x0]
- 5.6.4.8 FLAG Register (subaddress = 0x7) [reset = 0x0]
- 5.6.4.9 PASSWORD Register (subaddress = 0x10) [reset = 0x0]
- 5.6.4.10 ENABLE1 Register (subaddress = 0x11) [reset = 0x0]
- 5.6.4.11 ENABLE2 Register (subaddress = 0x12) [reset = 0x0]
- 5.6.4.12 CONFIG1 Register (subaddress = 0x13) [reset = 0x4C]
- 5.6.4.13 CONFIG2 Register (subaddress = 0x14) [reset = 0xC0]
- 5.6.4.14 CONFIG3 Register (subaddress = 0x15) [reset = 0x0]
- 5.6.4.15 DCDC1 Register (offset = 0x16) [reset = 0x99]
- 5.6.4.16 DCDC2 Register (subaddress = 0x17) [reset = 0x99]
- 5.6.4.17 DCDC3 Register (subaddress = 0x18) [reset = 0x8C]
- 5.6.4.18 DCDC4 Register (subaddress = 0x19) [reset = 0xB2]
- 5.6.4.19 SLEW Register (subaddress = 0x1A) [reset = 0x6]
- 5.6.4.20 LDO1 Register (subaddress = 0x1B) [reset = 0x1F]
- 5.6.4.21 SEQ1 Register (subaddress = 0x20) [reset = 0x0]
- 5.6.4.22 SEQ2 Register (subaddress = 0x21) [reset = 0x0]
- 5.6.4.23 SEQ3 Register (subaddress = 0x22) [reset = 0x98]
- 5.6.4.24 SEQ4 Register (subaddress = 0x23) [reset = 0x75]
- 5.6.4.25 SEQ5 Register (subaddress = 0x24) [reset = 0x12]
- 5.6.4.26 SEQ6 Register (subaddress = 0x25) [reset = 0x63]
- 5.6.4.27 SEQ7 Register (subaddress = 0x26) [reset = 0x3]
- 6 Application and Implementation
- 7 Power Supply Recommendations
- 8 Layout
- 9 器件和文檔支持
- 10機械、封裝和可訂購信息
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
訂購信息
5.3.1.1 Power-Up Sequencing
When the power-up sequence initiates, STROBE1 occurs, and any rail assigned to this strobe is enabled. After a delay time of DLY1, STROBE2 occurs and the rail assigned to this strobe is powered up. The sequence continues until all strobes occur and all DLYx times execute. Strobe assignments and delay times are defined in the SEQx registers, and are changed under I2C control. The power-up sequence executes if one of the following events occurs:
- From the OFF state:
- The push-button (PB) is pressed (falling edge on PB) OR
- The AC_DET pin is pulled low (falling edge) OR
- The PWR_EN is asserted (driven to high-level) OR
- The main power is connected (IN_BIAS) and AC_DET is grounded AND
- The device is not in undervoltage lockout (UVLO) or overtemperature shutdown (OTS).
- From the PRE_OFF state:
- The PB is pressed (falling edge on PB) OR
- The AC_DET pin is pulled low (falling edge) OR
- PWR_EN is asserted (driven to high-level) AND
- The device is not in UVLO or OTS.
- From the SUSPEND state:
- The PB is pressed (falling edge on PB) OR
- The AC_DET pin is pulled low (falling edge) OR
- The PWR_EN pin is pulled high (level sensitive) AND
- The device is not in UVLO or OTS.
When a power-up event is detected, the device enters a WAIT_PWR_EN state and triggers the power-up sequence. The device remains in WAIT_PWR_EN as long as the PWR_EN and either the PB or AC_DET pin are held low. If both, the PB and AC_DET return to logic-high state and the PWR_EN pin has not been asserted within 20 s of entering WAIT_PWR_EN state, the power-down sequence is triggered and the device returns to OFF state. Once PWR_EN is asserted, the device advances to ACTIVE state, which is functionally equivalent to WAIT_PWR_EN. However, the AC_DET pin is ignored and power-down is controlled by the PWR_EN pin only.
Rails not assigned to a strobe (SEQ = 0000b) are not affected by power-up and power-down sequencing and remain in their current ON/OFF state regardless of the sequencer. A rail can be enabled/disabled at any time by setting the corresponding enable bit in the ENABLEx register, with the exception that the ENABLEx register cannot be accessed while the sequencer is active. Enable bits always reflect the current enable state of the rail, for example the sequencer sets and resets the enable bits for the rails under its control.
NOTE
The power-up sequence is defined by strobes and delay times, and can be triggered by the PB, AC_DET (not shown, same as PB), or PWR_EN pin.
PB is Power-Up Event
Figure 5-2 Power-Up Sequences from SUSPEND State;
PWR_EN is Power-Up Event
Figure 5-3 Power-Up Sequences from RECOVERY State