ZHCSM96A November 2020 – August 2021 TPS6521835
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1
Wake-Up and Power-Up and Power-Down Sequencing
- 7.3.1.1 Power-Up Sequencing
- 7.3.1.2 Power-Down Sequencing
- 7.3.1.3 Strobe 1 and Strobe 2
- 7.3.1.4 Supply Voltage Supervisor and Power-Good (PGOOD)
- 7.3.1.5 Backup Supply Power-Good (PGOOD_BU)
- 7.3.1.6 Internal LDO (INT_LDO)
- 7.3.1.7 Current Limited Load Switches
- 7.3.1.8 LDO1
- 7.3.1.9 Coin Cell Battery Voltage Acquisition
- 7.3.1.10 UVLO
- 7.3.1.11 Power-Fail Comparator
- 7.3.1.12 Battery-Backup Supply Power-Path
- 7.3.1.13 DCDC3 and DCDC4 Power-Up Default Selection
- 7.3.1.14 I/O Configuration
- 7.3.1.15 Push Button Input (PB)
- 7.3.1.16 AC_DET Input (AC_DET)
- 7.3.1.17 Interrupt Pin (INT)
- 7.3.1.18 I2C Bus Operation
- 7.3.1
Wake-Up and Power-Up and Power-Down Sequencing
- 7.4 Device Functional Modes
- 7.5 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
7.3.1.14.2 Using GPIO3 as Reset Signal to DCDC1 and DCDC2
The GPIO3 is an edge-sensitive reset input to the PMIC, when the DC12_RST bit set to 1. The reset signal affects DCDC1 and DCDC2 only, so that only those two registers are reset to the power-up default whenever GPIO3 input transitions from high to low, while all other registers maintain their current values. DCDC1 and DCDC2 transition back to the default value following the SLEW settings, and are not power cycled. This function recovers the processor from reset events while in low-power mode.
Figure 7-24 I/O Pin
Logic
Figure 7-25 DDR3
Reset Timing DiagramGPIO must be configured as input (IO1_SEL = 1b). GPO2 is automatically configured as output.