ZHCSM96A November 2020 – August 2021 TPS6521835
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1
Wake-Up and Power-Up and Power-Down Sequencing
- 7.3.1.1 Power-Up Sequencing
- 7.3.1.2 Power-Down Sequencing
- 7.3.1.3 Strobe 1 and Strobe 2
- 7.3.1.4 Supply Voltage Supervisor and Power-Good (PGOOD)
- 7.3.1.5 Backup Supply Power-Good (PGOOD_BU)
- 7.3.1.6 Internal LDO (INT_LDO)
- 7.3.1.7 Current Limited Load Switches
- 7.3.1.8 LDO1
- 7.3.1.9 Coin Cell Battery Voltage Acquisition
- 7.3.1.10 UVLO
- 7.3.1.11 Power-Fail Comparator
- 7.3.1.12 Battery-Backup Supply Power-Path
- 7.3.1.13 DCDC3 and DCDC4 Power-Up Default Selection
- 7.3.1.14 I/O Configuration
- 7.3.1.15 Push Button Input (PB)
- 7.3.1.16 AC_DET Input (AC_DET)
- 7.3.1.17 Interrupt Pin (INT)
- 7.3.1.18 I2C Bus Operation
- 7.3.1
Wake-Up and Power-Up and Power-Down Sequencing
- 7.4 Device Functional Modes
- 7.5 Register Maps
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
7.3.1.12 Battery-Backup Supply Power-Path
DCDC5 and DCDC6 are supplied from either the CC (coin-cell battery) input or IN_BU (main system supply). The power-path is designed to prioritize IN_BU to maximize coin-cell battery life. Whenever the PMIC is powered-up (WAIT_PWR_EN, ACTIVE, SUSPEND, and RECOVERY state), the power-path is forced to select the IN_BU input. In OFF mode the power-path selects the higher of the two inputs with a built-in hysteresis of 150 mV as shown in #SLDS2069376.
Figure 7-18 Switching Behavior of the Battery-Backup-Supply Power-Path; Power-Path
Hysteresis
When VIN_BIAS drops below the UVLO threshold, the PMIC shuts down all rails and enters OFF mode. At this point the power-path selects the higher of the two input supplies. If the coin-cell battery is less than 150 mV above the UVLO threshold, SYS_BU remains connected to IN_BU (see #X4173). If the coin-cell is >150 mV above the UVLO threshold, the power-path switches to the CC input as shown in #X126. With no load on the main supply, the input voltage may recover over time to a value greater than the coin-cell voltage and the power-path switches back to IN_BU. This is a typical behavior in a Li-Ion battery powered system.
Depending on the system load, VIN_BIAS may drop below VINT_LDO before the power-down sequence is completed. In that case, INT_LDO is turned OFF and the digital core is reset forcing the unit into OFF mode and the power-path switches to IN_BU as shown in #X5266.