ZHCSKD3A November 2019 – February 2021 TPS6521815
PRODUCTION DATA
The device has two GPIOs and one GPO pin, which are configured as follows:
| IO1_SEL (EEPROM) | GPO1 (USER BIT) | PGOOD (PMIC SIGNAL) | GPIO1 (I/O PIN) | COMMENTS |
|---|---|---|---|---|
| 0 | 0 | X | 0 | Open-drain output, driving low |
| 0 | 1 | X | HiZ | Open-drain output, HiZ |
| IO1_SEL (EEPROM) | GPO2_BUF (EEPROM) | GPO2 (USER BIT) | COMMENTS |
|---|---|---|---|
| 0 | 0 | 0 | GPO2 is open drain output controlled by GPO2 user bit (driving low). |
| 0 | 0 | 1 | GPO2 is open drain output controlled by GPO2 user bit (HiZ). |
| 0 | 1 | 0 | GPO2 is push-pull output controlled by GPO2 user bit (driving low). |
| 0 | 1 | 1 | GPO2 is push-pull output controlled by GPO2 user bit (driving high). |
| 1 | 0 | X | GPO2 is open drain output controlled by GPIO1 and PGOOD. |
| 1 | 1 | X | GPO2 is push-pull output controlled by GPIO1 and PGOOD. |
| DC12_RST (EEPROM) | GPO3 (USER BIT) | GPIO3 (I/O PIN) | COMMENTS |
|---|---|---|---|
| 0 | 0 | 0 | Open-drain output, driving low |
| 0 | 1 | HiZ | Open-drain output, HiZ |
| 1 | X | Active low | GPIO3 is DCDC1 and DCDC2 reset input signal to PMIC (active low). See Section 8.3.1.14.2 for details. |