ZHCSKD3A November 2019 – February 2021 TPS6521815
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Description (continued)
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1
Wake-Up and Power-Up and Power-Down Sequencing
- 8.3.1.1 Power-Up Sequencing
- 8.3.1.2 Power-Down Sequencing
- 8.3.1.3 Strobe 1 and Strobe 2
- 8.3.1.4 Supply Voltage Supervisor and Power-Good (PGOOD)
- 8.3.1.5 Backup Supply Power-Good (PGOOD_BU)
- 8.3.1.6 Internal LDO (INT_LDO)
- 8.3.1.7 Current Limited Load Switches
- 8.3.1.8 LDO1
- 8.3.1.9 Coin Cell Battery Voltage Acquisition
- 8.3.1.10 UVLO
- 8.3.1.11 Power-Fail Comparator
- 8.3.1.12 Battery-Backup Supply Power-Path
- 8.3.1.13 DCDC3 and DCDC4 Power-Up Default Selection
- 8.3.1.14 I/O Configuration
- 8.3.1.15 Push Button Input (PB)
- 8.3.1.16 AC_DET Input (AC_DET)
- 8.3.1.17 Interrupt Pin (INT)
- 8.3.1.18 I2C Bus Operation
- 8.3.1
Wake-Up and Power-Up and Power-Down Sequencing
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6 Register Maps
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.3.1.13 DCDC3 and DCDC4 Power-Up Default Selection
Figure 8-21 Left: Flow Chart for Selecting DCDC Power-Up Default Voltage Right: Comparator CircuitTable 8-2 Power-Up Default Values of DCDC3 and DCDC4
| RSEL [KΩ] | POWER-UP DEFAULT | |||
|---|---|---|---|---|
| MIN | TYP | MAX | DCDC3[5:0] | DCDC4[5:0] |
| 0 | 0 | 7.7 | Programmed default (1.2 V) | Programmed default (3.3 V) |
| 11.8 | 12.1 | 12.4 | 0x12 (1.35 V) | Programmed default (3.3 V) |
| 19.5 | 20 | 20.5 | 0x18 (1.5 V) | Programmed default (3.3 V) |
| 30.9 | 31.6 | 32.3 | 0x1F (1.8 V) | Programmed default (3.3 V) |
| 44.4 | 45.3 | 46.3 | 0x3D (3.3 V) | 0x01 (1.2 V) |
| 64.8 | 66.1 | 67.3 | Programmed default (1.2 V) | 0x07 (1.35 V) |
| 93.6 | 95.3 | 97.2 | Programmed default (1.2 V) | 0x0D (1.5 V) |
| 146 | 150 | Tied to INT_LDO | Programmed default (1.2 V) | 0x14 (1.8 V) |