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ZHCS688I November 2011 – March 2018 TPS65217

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RSL|48
- MPQF193B

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

RSL|48
- QFND160L

訂購(gòu)信息

8.6.1 Register Address Map

Figure 29 lists the memory-mapped registers for the device registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified.

Figure 29. Register Address Map

Address (Decimal)	Address (Hexadecimal)	Name	Password Protection Level	Default Value	Description	Section
0	0x00	CHIPID	None	X	Chip ID	Go
1	0x01	PPATH	None	0x3D	Power path control	Go
2	0x02	INT	None	0x80	Interrupt flags and masks	Go
3	0x03	CHGCONFIG0	None	0x00	Charger control register 0	Go
4	0x04	CHGCONFIG1	None	0xB1	Charger control register 1	Go
5	0x05	CHGCONFIG2	None	0x80	Charger control register 2	Go
6	0x06	CHGCONFIG3	None	0xB2	Charger control register 3	Go
7	0x07	WLEDCTRL1	None	0xB1	WLED control register	Go
8	0x08	WLEDCTRL2	None	0x00	WLED PWM duty cycle	Go
9	0x09	MUXCTRL	None	0x00	Analog multiplexer control register	Go
10	0x0A	STATUS	None	0x00	Status register	Go
11	0x0B	PASSWORD	None	0x00	Write password	Go
12	0x0C	PGOOD	None	0x00	Power good (PG) flags	Go
13	0x0D	DEFPG	Level1	0x0C	Power good (PG) delay	Go
14	0x0E	DEFDCDC1	Level2	X	DCDC1 voltage adjustment	Go
15	0x0F	DEFDCDC2	Level2	X	DCDC2 voltage adjustment	Go
16	0x10	DEFDCDC3	Level2	0x08	DCDC3 voltage adjustment	Go
17	0x11	DEFSLEW	Level2	0x06	Slew control for DCDC1, DCDC2, DCDC3, and PFM mode enable	Go
18	0x12	DEFLDO1	Level2	0x09	LDO1 voltage adjustment	Go
19	0x13	DEFLDO2	Level2	0x38	LDO2 voltage adjustment	Go
20	0x14	DEFLS1	Level2	X	LS1 or LDO3 voltage adjustment	Go
21	0x15	DEFLS2	Level2	X	LS2 or LDO4 voltage adjustment	Go
22	0x16	ENABLE	Level1	0x00	Enable register	Go
23	0x18	DEFUVLO	Level1	0x03	UVLO control register	Go
24	0x19	SEQ1	Level1	X	Power-up STROBE definition	Go
25	0x1A	SEQ2	Level1	X	Power-up STROBE definition	Go
26	0x1B	SEQ3	Level1	X	Power-up STROBE definition	Go
27	0x1C	SEQ4	Level1	0x40	Power-up STROBE definition	Go
28	0x1D	SEQ5	Level1	X	Power-up delay times	Go
29	0x1E	SEQ6	Level1	0x00	Power-up delay times	Go

Bit access types are abbreviated to fit into small table cells. Table 1 shows the abbreviation codes that are used for access types in this section. Registers that are different for each TPS65217x variant will have different hexadecimal reset values and are shown as X. The hexadecimal reset value can de determined by converting the binary reset value.

Table 1. Access Type Codes

Access Type⁽¹⁾	Code	Description
Read	R	Read-only
Read/Write	R/W	Read and Write

(1) Reserved bits can be R or R/W. Read-only (R) Reserved bits are not used and writing data to these bits will have no effect on device operation. Read and Write (R/W) Reserved bits are settings that cannot be modified. The reset value must always be written to these bits. Modifying a R/W Reserved bit will have an impact on device operation and can produce unwanted device behavior.