8.3.2 Power Good
The power-good signals are used to indicate if an output rail is in regulation or at fault. Internally, all power-good signals of the enabled rails are monitored at all times and if any of the signals goes low, a fault is declared. All power-good signals are internally deglitched. When a fault occurs, all output rails are powered down and the device goes to the OFF state.
The TPS65217x device has two power-good output pins: one is dedicated to the LDO1 and LDO2 rails (LDO_PGOOD) and one for all other rails (PGOOD). The power-good signals that are indicated by the PGOOD pin are programmable. The following rules apply to both output pins:
- The power-up default state for the PGOOD pin and the LDO_PGOOD pin is low. When all rails are disabled, the PGOOD and LDO_PGOOD pins are both low.
- Only enabled rails are monitored. Disabled rails are ignored.
- Power-good monitoring of a particular rail starts 5 ms after the rail has been enabled. The power-good signal is continuously monitored after the 5-ms deglitch time expires.
- The signals controlling the PGOOD and LDO_PGOOD pins are delayed by the PGDLY (20 ms default) after the sequencer is done.
- If a fault occurs on an enabled rail (such as a shorted output, OTS condition, or UVLO condition), the PGOOD pin, LDO_PGOOD pin, or both pins are pulled low, and all rails are shut down.
- If the user disables a rail (either manually or through the sequencer), this action has no effect on the PGOOD or LDO_PGOOD pin.
- If the user disables all rails (either manually or through the sequencer), the PGOOD pin, LDO_PGOOD pin, or both pins are pulled low.