ZHCS688I November 2011 – March 2018 TPS65217
PRODUCTION DATA.
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| fSCL | Serial clock frequency | 100 | 400 | kHz | ||
| tHD;STA | Hold time (repeated) START condition. After this period, the first clock pulse is generated | SCL = 100 KHz | 4 | µs | ||
| SCL = 400 KHz | 600 | ns | ||||
| tLOW | LOW period of the SCL clock | SCL = 100 KHz | 4.7 | µs | ||
| SCL = 400 KHz | 1.3 | |||||
| tHIGH | HIGH period of the SCL clock | SCL = 100 KHz | 4 | µs | ||
| SCL = 400 KHz | 600 | ns | ||||
| tSU;STA | Set-up time for a repeated START condition | SCL = 100 KHz | 4.7 | µs | ||
| SCL = 400 KHz | 600 | ns | ||||
| tHD;DAT | Data hold time | SCL = 100 KHz | 0 | 3.45 | µs | |
| SCL = 400 KHz | 0 | 900 | ns | |||
| tSU;DAT | Data set-up time | SCL = 100 KHz | 250 | ns | ||
| SCL = 400 KHz | 100 | |||||
| tr | Rise time of both SDA and SCL signals | SCL = 100 KHz | 1000 | ns | ||
| SCL = 400 KHz | 300 | |||||
| tf | Fall time of both SDA and SCL signals | SCL = 100 KHz | 300 | ns | ||
| SCL = 400 KHz | 300 | |||||
| tSU;STO | Set-up time for STOP condition | SCL = 100 KHz | 4 | µs | ||
| SCL = 400 KHz | 600 | ns | ||||
| tBUF | Bus free time between stop and start condition | SCL = 100 KHz | 4.7 | µs | ||
| SCL = 400 KHz | 1.3 | |||||
| tSP | Pulse duratoin of spikes which mst be suppressed by the input filter | SCL = 100 KHz | NA | NA | ||
| SCL = 400 KHz | 0 | 50 | ns | |||
| Cb | Capacitive load for each bus line | SCL = 100 KHz | 400 | pF | ||
| SCL = 400 KHz | 400 | |||||
Figure 1. I2C Data Transmission Timing