| POWER SUPPLY |
| IIN |
Supply current into VIN pin |
Converters not switching |
|
0.1 |
1 |
mA |
| IAVDD |
Supply current into AVDD pins |
Pins 2 and 3 connected together |
|
0.75 |
2.5 |
mA |
| IBSUP |
Supply current into BSUP pin |
|
|
2.5 |
5 |
mA |
| IGH |
Supply current into VGH pin |
No load on VGHM |
|
0.1 |
1 |
mA |
| UNDERVOLTAGE LOCKOUT |
| VUVLO |
Undervoltage lockout threshold |
VIN falling |
1.75 |
|
|
V |
| VIN rising |
|
|
2.2 |
| Hysteresis |
|
90 |
|
|
mV |
| LINEAR REGULATOR (VCC) |
| VCC |
Linear regulator output voltage range |
|
1.0 |
|
2.5 |
V |
| Tolerance |
ICC = 10 mA |
–3% |
|
+3% |
|
| VUVP |
Undervoltage protection threshold |
VCC falling |
60% |
70% |
75% |
|
| VSCP |
Short circuit protection threshold |
VCC falling |
25% |
30% |
40% |
|
| ILIM |
Current limit |
VCC = 5% below value at 10 mA. |
TJ = 25°C to 125°C |
300 |
|
|
mA |
| TJ = –40°C |
250 |
|
|
| rDS(ON) |
Active pull-down resistance |
|
10 |
21 |
35 |
Ω |
| BOOST CONVERTER 1 (AVDD) |
| AVDD |
Output voltage range |
|
6.5 |
|
9.6 |
V |
| Tolerance |
|
–2% |
|
+2% |
|
| VUVP |
Undervoltage protection threshold |
|
60% |
70% |
75% |
|
| VSCP |
Short-circuit protection threshold |
|
25% |
30% |
35% |
|
| rDS(ON) |
Switch ON resistance |
ISW = 1 A |
|
0.1 |
0.25 |
Ω |
| ILIM |
Switch current limit |
|
2.4 |
3.0 |
3.6 |
A |
| rDS(ON) |
Rectifier ON resistance |
ISW = 1 A |
|
0.25 |
0.4 |
Ω |
| fSW |
Switching frequency |
|
400 |
|
1000 |
kHz |
| Tolerance |
|
–20% |
|
+20% |
|
| NEGATIVE CHARGE PUMP (VGL) |
|
| VGL |
Output voltage range |
|
–5 |
|
–8 |
V |
| Output voltage tolerance |
|
–3% |
|
3.5% |
|
| VUVP |
Undervoltage protection threshold |
VGL rising |
65% |
70% |
75% |
|
| VSCP |
Short-circuit protection threshold |
VGL rising |
25% |
30% |
35% |
|
| IDRVN |
Maximum drive current |
C1B sinking |
50 |
|
150 |
mA |
| C1B sourcing |
60 |
|
160 |
| VDO |
Dropout voltage |
fSW = 500 kHz, CFLY = 0.5 µF, IGL = 10 mA |
|
0.6 |
1.0 |
V |
| fSW |
Switching frequency |
|
400 |
500 |
600 |
kHz |
| rDS(ON) |
Discharge ON resistance |
IMEAS = 2 mA |
2.1 |
3 |
3.9 |
kΩ |
| BOOST CONVERTER 2 (VGH) |
| VGH |
Output voltage range |
|
18 |
|
25.5 |
V |
| Tolerance |
|
–3% |
|
3% |
|
| VUVP |
Undervoltage protection threshold |
VGH falling |
65% |
70% |
75% |
|
| VSCP |
Short-circuit protection threshold |
VGH falling |
25% |
30% |
35% |
|
| rDS(ON) |
Switch ON resistance |
ISW = 1 A |
|
0.3 |
1.0 |
Ω |
| tON(MAX) |
Maximum tON time |
|
1 |
2 |
2.5 |
µs |
| tOFF |
tOFF time |
|
2 |
2.7 |
4 |
µs |
| BOOST CONVERTER 3 |
| VOUT |
Output voltage range |
|
VLED+2 |
|
38 |
V |
| ILIM |
Switch current limit |
|
2.0 |
2.7 |
3.7 |
A |
| rDS(ON) |
Switch ON resistance |
ISW = 1 A |
|
0.2 |
0.35 |
Ω |
| VOVP |
OVP range |
|
30 |
|
39 |
V |
| Tolerance |
|
-5% |
|
+5% |
|
| VIL |
EN low input voltage |
EN falling |
|
|
0.6 |
V |
| VIH |
EN high input voltage |
EN rising |
1.5 |
|
|
V |
| VIH – VIL |
EN input hysteresis |
|
0.09 |
0.16 |
0.27 |
V |
| RPULL-DOWN |
EN pull-down resistance |
|
450 |
750 |
1250 |
kΩ |
| WLED DIMMING |
| IFB |
Maximum current |
|
40 |
|
|
mA |
| Channel-to-channel current matching |
|
–3% |
|
+3% |
|
|
Output dimming resolution |
|
|
10 |
|
bits |
| DMIN |
Minimum output duty cycle |
|
|
|
1% |
|
| DHYS |
Input PWM jitter hysteresis |
|
–0.048% |
|
0.048% |
|
| VSET |
ISET regulation voltage |
|
–3% |
1.0 |
+3% |
V |
| KSET |
ISET multiplication constant |
|
1260 |
1296 |
1332 |
|
| VIL |
PWM low input voltage |
PWM falling |
|
|
0.6 |
V |
| VIH |
PWM high input voltage |
PWM rising |
1.2 |
|
|
V |
| VIH – VIL |
PWM input voltage hysteresis |
|
0.09 |
0.16 |
0.27 |
V |
| RPULL-DOWN |
PWM pull-down resistance |
|
450 |
750 |
1250 |
kΩ |
| RESET (RST) |
| VOL |
Output voltage |
IRST = 1 mA (sinking) |
|
0.2 |
0.5 |
V |
| IOH |
Leakage current |
VRST = 1.8 V |
|
|
1 |
µA |
| PROGRAMMABLE VCOM |
| SETZSE |
VCOM DAC set zero-scale error |
VMIN = 07h, VMAX = 07h |
−7 |
|
7 |
LSB |
| VMAX DAC set zero-scale error |
|
–1 |
|
1 |
| VMIN DAC set zero-scale error |
|
–1 |
|
1 |
| SETFSE |
VCOM set full-scale error |
VMIN = 07h, VMAX = 07h |
−7 |
|
7 |
LSB |
| VMAX set full-scale error |
|
–1 |
|
1 |
| VMIN set full-scale error |
|
−1 |
|
1 |
| DNL |
Differential nonlinearity |
VCOM |
|
|
1 |
LSB |
| VMAX |
|
|
1 |
| VMIN |
|
|
1 |
| BW |
Small-signal bandwidth |
Closed-loop; AV = –1; RF = 1 kΩ, RIN = 1 kΩ, VCM = 4 V; VSIGNAL = 63 mVpp; RL = ∞ |
|
21 |
|
MHz |
| IOUT |
Peak output current |
Open-loop; VPOS = 4 V, VNEG = 3 V |
|
400 |
|
mA |
| Open-loop; VPOS = 4 V, VNEG = –5 V |
|
330 |
|
| SR |
Slew rate |
Open-loop; VPOS = 4 V, VNEG = 5 V |
|
36 |
|
V/µs |
| Open-loop; VPOS = 4 V, VNEG = 3 V |
|
33 |
|
| IIB– |
Input bias current (inverting input) |
Closed-loop; AV = +1; RF = 1 MΩ; VPOS = 4 V |
−1 |
|
1 |
μA |
| VDROP |
Output voltage drop |
Open-loop; VPOS = 4 V; IMEAS = 10 mA |
VNEG = 3 V |
|
0.06 |
0.1 |
V |
| VNEG = 5 V |
|
0.03 |
0.1 |
| GATE VOLTAGE SHAPING |
| rDS(ON)H |
VGH to VGHM ON resistance |
VGH = 20 V, IGHM = 10 mA, VFLK = 1.8 V |
|
13 |
25 |
Ω |
| rDS(ON)L |
VGHM to RE ON resistance |
VGHM = 20 V, IGHM = 10 mA, VFLK = 0 V |
|
26 |
50 |
Ω |
| VGHM = 6 V, IGHM = 10 mA, VFLK = 0 V |
|
26 |
50 |
| VIL |
FLK low input voltage threshold |
VFLK falling |
0.6 |
|
|
V |
| VIH |
FLK high input voltage threshold |
VFLK rising |
|
|
1.2 |
V |
| VIH – VIL |
FLK input hysteresis |
|
0.09 |
0.15 |
0.27 |
V |
| IIL |
FLK low input current |
VFLK = 0 V |
–100 |
|
100 |
nA |
| IIH |
FLK high input current |
VFLK = 1.8 V |
–100 |
|
100 |
nA |
| PANEL RESET (XAO) |
| VOL(XAO) |
Output voltage |
IXAO = 1 mA (sinking) |
|
0.16 |
0.5 |
V |
| ILK(XAO) |
Leakage current |
VXAO = 1.8 V |
|
|
1 |
µA |
| VDET |
XAO Threshold voltage range |
VIN falling |
VUVLO |
|
3.0 |
V |
| Tolerance |
–3% |
|
+3% |
|
| Hysteresis |
VIN rising |
0.05 |
|
0.3 |
V |
| I2C INTERFACE |
| ADDR |
Configuration parameters slave address |
|
|
74h |
|
|
| Programmable VCOM slave address |
|
|
28h |
|
| VIL |
Low level input voltage |
SCL or SDA falling, standard and fast modes |
|
|
0.6 |
V |
| VIH |
High level input voltage |
SCL or SDA rising, standard and fast modes |
1.0 |
|
|
V |
| VIH – VIL |
Input hysteresis |
|
0.05 |
|
|
V |
| VOL |
Low level output voltage |
Sinking 3 mA |
|
|
0.36 |
V |
| CI |
Input capacitance |
|
|
|
10 |
pF |
| CB |
Capacitive load on SDA and SCL |
Standard mode |
|
|
400 |
pF |
| Fast mode |
|
|
400 |
| EEPROM |
| VIL |
WP low input voltage threshold |
VWP falling |
0.8 |
|
|
V |
| VIH |
WP high input voltage threshold |
VWP rising |
|
|
1.2 |
V |
| VIH – VIL |
WP input voltage hysteresis |
|
0.03 |
0.05 |
0.1 |
V |
| RPULL-UP |
WP internal pull-up resistor |
|
20 |
60 |
100 |
kΩ |
| NWRITE |
Number of write cycles |
|
1000 |
|
|
|
|
Data retention |
Storage temperature = 150 °C |
100 |
|
|
1000 hrs |
| THERMAL SHUTDOWN |
| TSD |
Thermal shutdown temperature |
|
|
150 |
|
°C |
| Thermal shutdown hysteresis |
|
|
10 |
|