ZHCSFJ2F September 2015 – January 2025 TPS65094
PRODUCTION DATA
When a valid power source is available at VSYS (VSYS ≥ 5.6 V), internal analog blocks including LDO5 and LDO3P3 are enabled. For part numbers with LDOA1 set as an always on rail, the PMIC leaves reset and I2C communication is available as soon as LDO3P3 and LDO5 power goods are confirmed. For part numbers with LDOA1 set as a general-purpose LDO, the PMIC remains in reset until PMICEN is set high. Five input pins of the TPS65094x device are driven by a host or by external-controller (EC) defined power states that transition from one to another in sequence.
Table 7-8 shows various system-level power states. Also, Table 7-9 summarizes a list of active rails in each power state. The sequencing for the transitions between these states is described in the following sections.
If a rail is either disabled by I2C or OTP programming, then it is not enabled by the following sequences. For example, VTT LDO is not enabled for LPDDR4 OTPs.
| POWER STATE | SIGNALS TO PMIC | SIGNALS FROM PMIC | ||||||
|---|---|---|---|---|---|---|---|---|
| PMICEN | SLP_S4B(1) | SLP_S3B(1) | SLP_S0B(2) | THERMTRIPB(3) | RSMRSTB | PCH_PWROK | ||
| G3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| S4/S5 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | |
| S3 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | |
| S0iX | 1 | 1 | 1 | 0 | 1 | 1 | 1 | |
| S0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
| POWER STATE | ACTIVE RAILS |
|---|---|
| S4/S5 | BUCK1 (VNN), BUCK4 (V1P8A), BUCK5 (V1P24A) |
| S3 | Rails in S4/S5 + SWB1_2 (V1P8U)(1), BUCK6 (VDDQ) |
| S0 | Rails in S3 + SWB1_2(2), VTT, BUCK2 (VCCGI), BUCK3 (VCCRAM) |
| S0iX | Rails in S0 – BUCK1 (VNN), BUCK2 (VCCGI), BUCK3 (VCCRAM), VTT |