TI recommends using ceramic capacitors with low ESR values to provide the lowest output voltage ripple. The output capacitor requires an X7R or an X5R dielectric. Y5V and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive at high frequencies.

At light load currents, the controller operates in PFM mode, and the output voltage ripple is dependent on the output-capacitor value and the PFM peak inductor current. Higher output-capacitor values minimize the voltage ripple in PFM mode. To achieve specified regulation performance and low output voltage ripple, the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of ceramic capacitors drops with increasing DC bias voltage.

TI recommends the use of small ceramic capacitors placed between the inductor and load with many vias to the PGND plane for the output capacitors of the BUCK controllers. This solution typically provides the smallest and lowest cost solution available for D-CAP2 controllers.

The selection of the output capacitor is typically driven by the output transient response. Equation 7 and Equation 8 provide a rough estimate of the minimum required capacitance to ensure proper transient response. Because the transient response is significantly affected by the board layout, some experimentation is expected in order to confirm that values derived in this section are applicable to any particular use case. These are not meant to be an absolute requirement, but rather a rough starting point. Alternatively, some known combination values from which to begin are provided in Table 8-1. V_UNDER and V_OVER values must be greater than or equal to 3% of V_OUT setting in order for equations to be meaningful. The equations provide some margin so that actual capacitance requirement may be lower than calculated.

Equation 7.

where

• I_TRAN(max) is the maximum load current step
• L is the chosen inductance
• V_IN is the maximum input voltage
• V_OUT is the minimum programmed output voltage
• V_UNDER is the maximum allowable undershoot from programmed voltage

Equation 8.

where

• V_OVER is the maximum allowable overshoot from programmed voltage

Another key performance factor can be the ripple voltage while in pulsed frequency modulation mode, also known as discontinuous conduction mode. At light load, the controller disables the low side FET once it detects a zero-crossing event on the inductor current. The low side FET stays disabled until V_OUT crosses below the set VID threshold. This architecture allows significant power savings at light load conditions by minimizing power loss through the low side FET and through switching. The disadvantage is that there is higher voltage ripple since the ripple current is only positive. Additionally, for even higher efficiency, T_ON(PFM) for this device is typically 80% longer than T_ON(PWM), which can be calculated by dividing the duty cycle by the switching frequency. An estimate for the required capacitance for a given allowable ripple voltage at light load is shown in Equation 9. ESR of the output capacitor is neglected here because ceramic capacitors, which typically have low ESR, are recommended. V_OVER must not be set lower than 3% of V_OUT value.

Equation 9.

where

• T_{ON_EXT} is the PFM on time extension constant, 1.8 unless otherwise noted in the part number specific section
• V_OUT is the maximum programmed output voltage
• V_IN is the maximum input voltage
• f_SW is the typical switching frequency when loaded, 1 MHz unless otherwise noted
• V_OVER is the maximum allowable overshoot from programmed voltage
• L is the chosen inductance

In cases where the transient current change is very low and ripple voltage allowance is large, the DC stability may become important. DCAP2 is a very stable architecture so this value is likely to be the smallest of those calculated. Equation 10 approximates the amount of capacitance necessary to maintain DC stability. Again, this is provided as a starting point; actual values vary on a board-to-board case.

Equation 10.

where

• V_OUT is the maximum programmed output voltage
• 50μs is based on internal ramp setup
• V_IN is the minimum input voltage
• f_SW is the typical switching frequency
• L is the chosen inductance

Choosing the maximum valuable between Equation 7, Equation 8, Equation 9, and Equation 10 is recommended as a starting point to get the desired performance. All equations are estimates and have not been validated at all variable corners. Removing excess capacitance or adding extra capacitance may be necessary during board evaluation. Testing can typically be performed on the evaluation module or on prototype boards.