ZHCSG44G June 2017 – January 2025 TPS650864
PRODUCTION DATA
A delay can be added to the enable of any rail after the desired CTLx and PGs are met. Adding a delay allows for the option to create additional timing groups from either CTLx pins or internal PGs. For a demonstration of this feature, Figure 7-24 shows how BUCK2 and BUCK6 are enabled after BUCK1 is enabled from CTL1 pin.