ZHCSG44G June 2017 – January 2025 TPS650864
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| BUCK3, BUCK4, BUCK5 | ||||||
| VIN | Power input voltage | 3.0 | 5.5 | V | ||
| VOUT | DC output voltage VID range and options | VID step size = 10mV, BUCKx_VID[6:0] progresses from 0000001 to 1111111 | 0.41 | See Section 4 | 1.67 | V |
| VID step size = 25mV, BUCKx_VID[6:0] progresses from 0000001 to 1111111 | 0.425 | See Section 4 | 3.575 | |||
| DC output voltage accuracy | VIN = 5.0V, VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3V, IOUT = 1.5A | –2% | 2% | |||
| VIN = 3.3V, VOUT = 1, 1.2, 1.35, 1.5, 1.8V, IOUT = 1.5A | –2% | 2% | ||||
| VIN = 5.0V, VOUT = 1, 1.2, 1.35, 1.5, 1.8V, 2.5, 3.3V, IOUT = 100mA | –2.5% | 2.5% | ||||
| VIN = 3.3V, VOUT = 1, 1.2, 1.35, 1.5, 1.8V, IOUT = 100mA | –2.5% | 2.5% | ||||
| VDCM | Total output voltage accuracy (DC + ripple) in DCM | VIN = 5.0V, IOUT = 10mA, VOUT ≤ 1V | –30 | 40 | mV | |
| SR(VOUT) | Output DVS slew rate | VID step size = 10mV | 2.5 | 3.125 | mV/μs | |
| VID step size = 25mV | 3.125 | 4 | ||||
| IOUT | Continuous DC output current | 3 | A | |||
| IIND_LIM | HSD FET current limit | 4.3 | 7 | A | ||
| IQ | Quiescent current | VIN = 5V, VOUT = 1V, BUCKx_MODE = 0b | 35 | μA | ||
| ΔVOUT/ΔVIN | Line regulation | VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3V, IOUT = 1.5A | –0.5% | 0.5% | ||
| ΔVOUT/ΔIOUT | Load regulation | VIN = 5V, VOUT = 1, 1.2, 1.35, 1.5, 1.8, 2.5, 3.3V, IOUT = 0A to 3A, referenced to VOUT at IOUT = 1.5A | –0.2% | 2% | ||
| VTH_PG | Power Good deassertion threshold in percentage of target VOUT | VOUT rising | 108% | |||
| VOUT falling | 92% | |||||
| VTH_HYS_PG | Power Good reassertion hysteresis entering back into VTH_PG | VOUT rising or falling | 3% | |||
| RDIS | Output auto-discharge resistance | BUCKx_DISCHG[1:0] = 01 | 100 | Ω | ||
| BUCKx_DISCHG[1:0] = 10 | 200 | |||||
| BUCKx_DISCHG[1:0] = 11 | 500 | |||||