ZHCSI15L June 2006 – May 2018 TPS65023 , TPS65023B
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3
- 6.7 Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO
- 6.8 Electrical Characteristics: VDCDC1 Step-Down Converter
- 6.9 Electrical Characteristics: VDCDC2 Step-Down Converter
- 6.10 Electrical Characteristics: VDCDC3 Step-Down Converter
- 6.11 I2C Timing Requirements for TPS65023B
- 6.12 Typical Characteristics
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 VRTC Output and Operation With or Without Backup Battery
- 7.3.2 Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
- 7.3.3 Power Save Mode Operation
- 7.3.4 Low Ripple Mode
- 7.3.5 Soft-Start
- 7.3.6 100% Duty Cycle Low Dropout Operation
- 7.3.7 Active Discharge When Disabled
- 7.3.8 Power-Good Monitoring
- 7.3.9 Low-Dropout Voltage Regulators
- 7.3.10 Undervoltage Lockout
- 7.3.11 Power-Up Sequencing
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1 VERSION Register Address: 00h (Read Only)
- 7.6.2 PGOODZ Register Address: 01h (Read Only)
- 7.6.3 MASK Register Address: 02h (Read and Write), Default Value: C0h
- 7.6.4 REG_CTRL Register Address: 03h (Read and Write), Default Value: FFh
- 7.6.5 CON_CTRL Register Address: 04h (Read and Write), Default Value: B1h
- 7.6.6 CON_CTRL2 Register Address: 05h (Read and Write), Default Value: 40h
- 7.6.7 DEFCORE Register Address: 06h (Read and Write), Default Value: 14h/1Eh
- 7.6.8 DEFSLEW Register Address: 07h (Read and Write), Default Value: 06h
- 7.6.9 LDO_CTRL Register Address: 08h (Read and Write), Default Value: Set with DEFLDO1 and DEFLDO2
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
封裝選項
請參考 PDF 數據表獲取器件具體的封裝圖。
機械數據 (封裝 | 引腳)
- RSB|40
散熱焊盤機械數據 (封裝 | 引腳)
- RSB|40
訂購信息
7.3.3 Power Save Mode Operation
As the load current decreases, the converters enter the power save mode operation. During PSM, the converters operate in a burst mode (PFM mode) with a frequency between 750 kHz and 2.25 MHz, nominal for one burst cycle. However, the frequency between different burst cycles depends on the actual load current and is typically far less than the switching frequency with a minimum quiescent current to maintain high efficiency.
To optimize the converter efficiency at light load, the average current is monitored and if in PWM mode the inductor current remains below a certain threshold, then PSM is entered. The typical threshold to enter PSM is calculated as shown in Equation 1, Equation 2 and Equation 3.
During the PSM the output voltage is monitored with a comparator, and by maximum skip burst width. As the output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on and the converter effectively delivers a constant current defined in Equation 4, Equation 5 and Equation 6.
If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage has again dropped below the threshold. The power save mode is exited, and the converter returns to PWM mode if either of the following conditions are met:
- the output voltage drops 2% below the nominal VO due to increasing load current
- the PFM burst time exceeds 16 × 1/fs (7.11 μs typical).
These control methods reduce the quiescent current to typically 14 μA per converter, and the switching activity to a minimum, thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal output voltage at light-load current results in a low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor. Increasing capacitor values makes the output ripple tend to zero. The PSM is disabled through the I2C interface to force the individual converters to stay in fixed frequency PWM mode.