ZHCSO00A March 2022 – March 2023 TPS629211-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY | ||||||
| IQ | Operating Quiescent Current, (Power Save Mode) | Iout = 0 mA, device not switching | 4 | μA | ||
| IQ;PWM | Operating Quiescent Current (PWM Mode) | VIN = 6V, VOUT=1.2V; Iout = 0 mA, device switching | 5 | mA | ||
| ISD | Shutdown current into VIN pin | EN = 0 V | 0.25 | 3 | μA | |
| VUVLO | Under Voltage Lock-Out | VIN rising | 2.85 | 2.95 | 3.0 | V |
| Under Voltage Lock-Out | VIN falling | 2.65 | 2.75 | 2.85 | V | |
| VUVLO | Under Voltage Lock-Out Hysteresis | 200 | mV | |||
| CONTROL & INTERFACE | ||||||
| ILKG | EN Input leakage current | EN=VIN | 3 | 300 | nA | |
| VIH;MODE | High-Level Input Voltage at MODE/S-CONF Pin | 1.0 | V | |||
| VIL;MODE | Low-level input voltage at MODE/S_CONF Pin | 0.15 | V | |||
| VIH | High-level input voltage at EN-Pin | 0.97 | 1.0 | 1.03 | V | |
| VIL | Low-level input voltage at EN-Pin | 0.87 | 0.9 | 0.93 | V | |
| VPG | Power good threshold | VFB rising, referenced to VFB nominal | 93% | 96% | 99% | |
| VFB falling, referenced to VFB nominal | 89% | 93% | 96% | |||
| VPG_HYS | Power good threshold hysteresis | hysteresis | 3% | |||
| tPG,DLY | Power good delay time | 32 | μs | |||
| tPG,DLY | Power good pull down resistance | 10 | ? | |||
| VPG,OL | Low-level output voltage at PG pin | ISINK = 1 mA | 0.1 | V | ||
| IPG,LKG | Input leakage current into PG pin | VPG = 5 V | 0.01 | 1 | μA | |
| POWER SWITCHES | ||||||
| RDS;ON | High-side FET on resistance | 250 | mΩ | |||
| Low-side FET on resistance | 85 | |||||
| ILIM | High-side FET current limit | 1.5 | 1.8 | 2.1 | A | |
| Low-side FET current limit | 1.3 | 1.6 | 1.9 | A | ||
| ILIM;SINK | Low-side FET sink current limit | 0.8 | 1 | 1.2 | A | |
| TSD | Thermal Shutdown Threshold | TJ rising | 170 | °C | ||
| Thermal Shutdown Hysteresis | TJ falling | 20 | ||||
| fSW | Switching frequency | 2.5-MHz selection (FPWM Mode) | 2.5 | MHz | ||
| fSW | Switching frequency | 1.0-MHz selection (FPWM Mode) | 1.0 | MHz | ||
| TON(MIN) | Minimum On-time | 40 | ns | |||
| ILKG;SW | Leakage current into SW-Pin | EN = 0V, VSW = VOS = 5.5V | 0.1 | 5 | μA | |
| OUTPUT | ||||||
| VO | Output Voltage Regulation | VSET Configuration selected, 0°C ≤ TJ ≤ 85°C | -1% | +1% | ||
| VO | Output Voltage Regulation | VSET Configuration selected, -40°C ≤ TJ ≤ 150°C (DRL Package) | -1.4% | +1.1% | ||
| VO | Output Voltage Regulation | VSET Configuration selected, VOUT ≤ 3.8V, -40°C ≤ TJ ≤ 150°C (DYC Package) |
-1.4% | +1.1% | ||
| VO | Output Voltage Regulation | VSET Configuration selected, VOUT ≥ 5.0V, -40°C ≤ TJ ≤ 150°C (DYC Package) |
-1.6% | +1.1% | ||
| VFB | Feedback Regulation Voltage | Adjustable Configuration selected | 0.6 | V | ||
| VFB | Feedback Voltage Regulation | FB-Option selected, 0°C ≤ TJ ≤ 85°C | -0.75% | +0.75% | ||
| VFB | Feedback Voltage Regulation | FB-Option selected, -40°C ≤ TJ ≤ 150°C | -1.2% | +0.75% | ||
| IFB | Input leakage current into FB pin | Adjustable configuration, VFB = 0.6 V | 1 | 100 | nA | |
| Tdelay | Start-up delay time | IO = 0 mA, time from EN rising edge until start switching, External FB Configuration selected | 700 | 1500 | μs | |
| Start-up delay time | IO = 0 mA, time from EN rising edge until start switching, VSET Configuration selected | 1000 | 1800 | μs | ||
| TSS | Soft-Start time | IO = 0 mA after Tdelay, from 1st switching pulse until target VO | 600 | 700 | μs | |
| RDISCH | Active Discharge Resistance | Discharge = ON - Option Selected, EN = LOW, | 7.5 | 20 | ? | |