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ZHCSLJ2B September 2020 – July 2021 TPS62868 , TPS62869

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RQY|9
- MPQF584

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

7.5 Electrical Characteristics

T_J = -40 °C to 125 °C, and V_IN = 2.4 V to 5.5 V. Typical values are at T_J = 25 °C and V_IN = 5 V, unless otherwise noted.

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY
I_Q	Quiescent current	TPS6286x1A/C, TPS6286x2A/C	EN = High, no load, device not switching		4	10	μA
I_Q	Quiescent current	TPS6286x0A/C	EN = High, no load, device not switching		9	15	μA
I_{Q_VOS}	Operating quiescent current into VOS pin		EN = High, no load, device not switching, V_VOS = 1.8 V		18		μA
I_SD	Shutdown current		EN = Low, T_J = –40°C to 85°C		0.24	1	μA
V_UVLO	Undervoltage lockout threshold		V_IN rising	2.2	2.3	2.4	V
V_UVLO	Undervoltage lockout threshold		V_IN falling	2.1	2.2	2.3	V
T_JW	Thermal warning threshold		T_J rising		130		°C
T_JW	Thermal warning hysteresis		T_J falling		20		°C
T_JSD	Thermal shutdown threshold		T_J rising		150		°C
T_JSD	Thermal shutdown hysteresis		T_J falling		20		°C
LOGIC INTERFACE EN, SDA, SCL
V_IH	High-level input threshold voltage at EN, SCL, SDA, VSET/VID			0.84			V
V_IL	Low-level input threshold voltage at EN, SCL, SDA, VSET/VID					0.4	V
I_SCL,LKG	Input leakage current into SCL pin				0.01	0.8	μA
I_SDA,LKG	Input leakage current into SDA pin				0.01	0.1	μA
I_EN,LKG	Input leakage current into EN pin				0.01	0.1	μA
C_SCL	Parasitic capacitance at SCL				1		pF
C_SDA	Parasitic capacitance at SDA				2.4		pF
STARTUP, POWER GOOD
t_Delay	Enable delay time	TPS6286xA	Time from EN high to device starts switching, R1 = 249k?	420	700	1100	μs
t_Delay	Enable delay time	TPS6286x0C	Time from EN high to device starts switching	100	350	900	μs
t_Ramp	Output voltage ramp time		Time from device starts switching to power good	0.85	1	1.5	ms
V_PG	Power good lower threshold⁽¹⁾		V_VOS referenced to V_OUT nominal	85	91	96	%
V_PG	Power good upper threshold		V_VOS referenced to V_OUT nominal	103	111	120	%
t_PG,DLY	Power good deglitch delay		Rising and falling edges		34		μs
OUTPUT
V_OUT	Output voltage accuracy		FPWM, no Load, T_J = 0℃ to 85℃	-1		1	%
V_OUT	Output voltage accuracy		FPWM, no Load	-2		2	%
I_VOS,LKG	Input leakage current into VOS pin		EN = Low, Output discharge disabled, V_VOS = 1.8 V, TPS6286x1A/C		0.2	2.5	μA
R_DIS	Output discharge resistor at VOS pin				3.5		?
	Load regulation		V_OUT = 0.9 V, FPWM		0.04		%/A
POWER SWITCH
R_DS(on)	High-side FET on-resistance				11		m?
R_DS(on)	Low-side FET on-resistance				10.5		m?
I_LIM	High-side FET forward current limit		TPS62868	5	5.5	6	A
	High-side FET forward current limit		TPS62869	7	7.7	8.5	A
	Low-side FET forward current limit		TPS62868		4.5		A
	Low-side FET forward current limit		TPS62869		6.5		A
	Low-side FET negative current limit		TPS62868, TPS62869		-3		A
f_SW	PWM switching frequency		I_OUT= 1 A, V_OUT = 0.9 V		2.4		MHz

(1) TPS6286x0A and TPS6286x00C device variants do not have a lower PG threshold. In these device variants the PG signal is high if the start-up ramp is complete and the output voltage is below the upper PG threshold.