ZHCSL99G September 2019 – January 2025 TPS62860 , TPS62861
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Register Map
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
7.3.5 Power Good (PG)
The built-in power-good (PG) signal indicates that the output voltage has reached the target and the device is ready. The PG signal can be used for start-up sequencing of multiple rails or to indicate any overload behavior on the output. The PG pin is an open-drain output that requires a pullup resistor to any voltage up to the recommended input voltage level. PG is low when the device is turned off due to EN or thermal shutdown. VIN must remain present for the PG pin to stay LOW. When applying VIN the first time, PG stays HIGH until the first enabling of the device.
If the power-good output is not used, TI recommends to tie to GND or leave open.
| LOGIC SIGNALS | PG STATUS | ||||
|---|---|---|---|---|---|
| VI | EN-PIN | THERMAL SHUTDOWN | VOUT | DVS TRANSITION ACTIVE | |
| VI > UVLO | HIGH | NO | VOUT on target | NO | High Impedance |
| YES | LOW | ||||
| VOUT < target | x | LOW | |||
| YES | x | x | LOW | ||
| LOW | x | x | x | LOW | |
| VI < UVLO | x | x | x | x | Undefined |
The PG indicator triggers immediately (after internal comparator delay) when VO crosses the lower VPGTH to indicate that the voltage has left the target setting. It features a delay after crossing the upper VPGTH when going high to make sure VO has reached the target again. Figure 7-2 sketches the behavior.
Figure 7-2 Power Good Transient and De-glitch BehaviorThe PG Indicator is by default pulled low during DVS transition of the output voltage without any blanking or delay time. Figure 7-2 shows an example of this behavior. After VO has reached the new target, the PG is again active as shown in Figure 7-2.