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ZHCSE11A June 2015 – June 2015 TPS62745 , TPS627451

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

DSS|12
- MPDS336C

散熱焊盤機械數據 (封裝 | 引腳)

DSS|12
- QFND199C

訂購信息

8 Specifications

8.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

	PIN	MIN	MAX	UNIT
Voltage	VIN	–0.3	12	V
	SW, VIN_SW⁽²⁾	–0.3	V_IN +0.3	V
	EN	–0.3	V_IN +0.3	V
	EN_VIN_SW, VSEL1-4	–0.3	6	V
	PG	–0.3	6	V
	VOUT	–0.3	3.6	V
Power Good Sink Current	PG		10	mA
V_IN Switch Output Current	VIN_SW		10	mA
Junction temperature, T_J		–40	150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The DC voltage on the SW pin must not exceed 3.6 V

8.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
Supply voltage V_IN		3.3		10	V
Output current I_OUT	V_OUT + 0.7 V ≤ V_IN ≤ 10 V			300	mA
Effective inductance		2.8	4.7	6.2	µH
Capacitance connected to VIN pin		3	10		µF
Total effective capacitance connected to VOUT pin ⁽¹⁾		5	10	22	µF
Operating junction temperature range, T_J		–40		125	°C
Operating ambient temperature range, T_A		–40		85	°C

(1) Due to the DC bias effect of ceramic capacitors, the effective capacitance is lower then the nominal value when a voltage is applied. This is why the capacitance is specified to allow the selection of the smallest capacitor required with the DC bias effect for this type of capacitor in mind. The nominal value given matches a typical capacitor to be chosen to meet the minimum capacitance required.

8.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS62745	UNIT
		DSS
		12 PINS
R_θJA	Junction-to-ambient thermal resistance	61.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	70.9	°C/W
R_θJB	Junction-to-board thermal resistance	25.7	°C/W
ψ_JT	Junction-to-top characterization parameter	1.9	°C/W
ψ_JB	Junction-to-board characterization parameter	25.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	7.2	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

V_IN = 6 V, T_J = –40°C to 125°C typical values are at T_J = 25°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
SUPPLY
V_IN	Input voltage range	V_OUT + 0.7 V ≤ V_IN ≤ 10 V ; min 3.3 V, whichever value is higher		3.3		10	V
I_Q	Operating quiescent current	EN = V_IN, device not switching; I_OUT = 0 µA; V_OUT = 2 V; T_J = –40°C to 85°C			400	1960	nA
I_SD	Shutdown current	EN = GND, shutdown current into V_IN; T_J = -40°C to 85°C			130	1200	nA
I_SD	Shutdown current	EN = GND, shutdown current into V_IN; T_J = 60°C				830	nA
V_{TH_}_UVLO+	Undervoltage lockout threshold	Rising V_IN; T_J = –40°C to 85°C			3.1	3.3	V
V_{TH_UVLO-}	Undervoltage lockout threshold	Falling V_IN; T_J = –40°C to 85°C			2.9	3.1	V
INPUTS (EN, EN_VIN_SW, VSEL1-4)
V_{IH TH}	High level input voltage	V_{TH_UVLO-} ≤ V_IN ≤ 10 V		1.2			V
V_{IL TH}	Low level input voltage	V_{TH_UVLO-} ≤ V_IN ≤ 10 V				0.35	V
I_IN	Input bias current; except EN pin	T_J = 25°C				10	nA
		T_J = 60°C				20
		T_J = –40°C to 85°C				50
I_IN	Input bias current for EN pin	T_J = 25°C				20	nA
		T_J = 60°C				40
		T_J = –40°C to 85°C				100
POWER SWITCHES
R_DS(ON)	High side MOSFET on-resistance	V_IN = 4 V, I = 140 mA			0.6	0.98	Ω
R_DS(ON)	Low side MOSFET on-resistance	V_IN = 4 V, I = 140 mA			0.5	0.85	Ω
I_LIMF	High side MOSFET DC switch current limit	3.6 V ≤ V_IN ≤ 10 V; device not in soft start		480	600	720	mA
I_LIMF	Low side MOSFET DC switch current limit	3.6 V ≤ V_IN ≤ 10 V; device not in soft start			600		mA
OUTPUT DISCHARGE SWITCH (VOUT)
R_{DSCH_VOUT}	MOSFET on-resistance	EN = GND, I_OUT = –10 mA into VOUT pin			25	60	Ω
I_{IN_VOUT}	Bias current into VOUT pin⁽¹⁾	EN = V_IN, V_OUT = 2 V	T_J = 25°C		40	100	nA
I_{IN_VOUT}	Bias current into VOUT pin⁽¹⁾	EN = V_IN, V_OUT = 2 V	T_J = –40°C to 85°C			500	nA
INPUT VOLTAGE SWITCH (VIN_SW)
R_DS(ON)	MOSFET on-resistance	EN_VIN_SW = High, I_{VIN_SW} = 1 mA			85	160	Ω
I_{VIN_SW_LKG}	VIN-switch leakage current	EN_VIN_SW = GND; leakage from VIN to VIN_SW when pulled to GND; T_J = –40°C to 85°C		-20		20	nA
I_{VIN_SW}	VIN-switch current					5	mA
POWER GOOD OUTPUT (PG)
V_{TH_PG+}	Power good threshold voltage	Rising output voltage on VOUT pin		95	97.5		%
V_{TH_HYS}	Power good threshold hysteresis	Falling output voltage on VOUT pin			3		%
V_OL	Low level output threshold	3.3 V ≤ V_IN ≤ 10 V, EN = GND, current into PG pin I_PG = 4 mA				0.3	V
V_OH	High level output threshold	3.3 V ≤ V_IN ≤ 10 V, EN = high, current into PG pin I_PG = 0 mA				6	V
I_{IN_PG}	Bias current into power good pin	PG pin is high impedance, VOUT = 2 V, EN = V_IN, I_OUT = 0 mA; T_J = –40°C to 85°C				20	nA
OUTPUT
I_{LIM_softstart}	Switch current limit during soft start	Current limit is reduced during soft start, T_J = –40°C to 85°C		40	110	180	mA
V_VOUT	Output voltage range	For TPS627450; output voltages are selected with pins VSEL1 - 4		1.8		3.3	V
	Output voltage range	For TPS627451; output voltages are selected with pins VSEL1 - 4		1.3		2.8	V
	Output voltage accuracy	PFM mode, I_OUT = 0 mA, V_OUT + 0.6 V ≤ V_IN ≤ 10 V; min 3.3 V, whichever value is higher; T_J = –40°C to 85°C		-2.5	0	2.5	%
	Output voltage accuracy	PWM Mode, V_OUT + 0.7 V ≤ V_IN ≤ 10 V; min 3.3 V, whichever value is higher; T_J = –40°C to 85°C		–2	0	2	%
	DC output voltage load regulation	V_OUT = 2.0 V; I_OUT = 2 mA to 80 mA (PFM mode)			0.005		%/mA
	DC output voltage load regulation	V_OUT = 2.0 V; I_OUT = 150 mA to 300 mA (PWM mode)			0.001		%/mA
	DC output voltage line regulation	V_OUT = 2.0 V, I_OUT = 300 mA, 4 V ≤ V_IN ≤ 10 V			0.015		%/V

(1) A 50-MΩ (typical) internal resistor divider is internally connected to the VOUT pin

8.6 Timing Characteristics

V_IN = 6 V, T_J = –40°C to 125°C typical values are at T_J = 25°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
SUPPLY
t_delay	UVLO delay time	response time of UVLO circuit	200		µs
INPUT VOLTAGE SWITCH (VIN_SW)
t_{VIN_SW}	VIN-switch turn-on settling time	Time from EN_VIN_SW = High until R_DS(ON) is within specification	100		µs
POWER GOOD OUTPUT (PG)
t_delay	PGOOD delay time	Response time of PGOOD circuit; falling edge	200		µs
OUTPUT
t_ONmin	Minimum ON time	V_IN = 6 V, V_OUT = 2.0 V, I_OUT = 0 mA	256		ns
t_OFFmin	Minimum OFF time	V_IN = 3.3 V	50		ns
t_Start	Regulator start up time	V_IN = 6 V, from transition EN = Low to High until device starts switching, T_J = -40°C to 85°C	15	50	ms
t_Softstart	Softstart time with reduced switch current limit	3.3 V ≤ V_IN ≤ 10 V, EN = V_IN	700		µs

8.7 Typical Characteristics

TPS62745 TPS627451 A38_TPS62745_Iq_vs_Vin.gif

EN = VIN, VOUT = 1.8 V, EN_VIN_SW = GND		Device Not Switching

Figure 1. Quiescent Current

TPS62745 TPS627451 A37_TPS62745_HSDrdson.gif

Figure 3. R_DS(ON) High-Side MOSFET

TPS62745 TPS627451 A39_TPS62745_Isd_vs_Vin.gif

EN = GND, EN_VIN_SW = GND

Figure 2. Shutdown Current

TPS62745 TPS627451 A40_ATPS62745_LSDrdson.gif

Figure 4. R_DS(ON) Low-Side MOSFET