ZHCSE11A June 2015 – June 2015 TPS62745 , TPS627451
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 典型應用電路原理圖
- 5 修訂歷史記錄
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
- 8 Specifications
- 9 Detailed Description
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機械、封裝和可訂購信息
9 Detailed Description
9.1 Overview
The TPS62745 is the first dual-cell, ultra low power step down converter combining TI's DCS-Control™ topology and ultra low quiescent current consumption (400 nA typical) while maintaining a regulated output voltage. The device extends high efficiency operation to output currents down to a few micro amperes.
9.2 Functional Block Diagram
9.3 Feature Description
9.3.1 DCS-Control™
TI's DCS-Control™ (Direct Control with Seamless Transition into Power Save Mode) is an advanced regulation topology, which combines the advantages of hysteretic and voltage mode control. Characteristics of DCS - ControlTM are excellent AC load regulation and transient response, low output ripple voltage and a seamless transition between pulse frequency modulation (PFM) and pulse width modulation (PWM) mode operation. DCS-ControlTM includes an AC loop which senses the output voltage (VOUT pin) and directly feeds the information to a fast comparator stage. This comparator sets the switching frequency, which is constant for steady state operating conditions, and provides immediate response to dynamic load changes. In order to achieve accurate DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves fast and stable operation with small external components and low ESR capacitors. The DCS-ControlTM topology supports PWM mode for medium and high load conditions and a power save mode at light loads. During PWM mode, it operates in continuous conduction. The switching frequency is up to 2.5 MHz with a controlled frequency variation depending on the input voltage. If the load current decreases, the converter seamlessly enters power save mode to maintain high efficiency down to very light loads. In power save mode the switching frequency varies linearly with the load current. Since DCS-ControlTM supports both operation modes within one single building block, the transition from PWM to power save mode is seamless without effects on the output voltage. The TPS62745 offers both excellent DC voltage and superior load transient regulation, combined with very low output voltage ripple, minimizing interference with RF circuits. At high load currents the converter operates in quasi fixed frequency PWM mode operation and at light loads in PFM mode to maintain highest efficiency over the full load current range. In PFM mode, the device generates a single switching pulse to ramp up the inductor current and recharge the output capacitor, followed by a sleep period where most of the internal circuits are shutdown to achieve a quiescent current of typically 400-nA. During this time, the load current is supported by the output capacitor. The duration of the sleep period depends on the load current and the inductor peak current.
9.3.2 Enable / Shutdown
The DC/DC converter is activated when EN pin is set to High. For proper operation, the pin must be terminated and must not be left floating. With EN pin set to Low, the device enters shutdown mode with typical 130 nA current consumption.
9.3.3 Power Good Output (PG)
The power good comparator features an open drain output. The PG comparator is active with EN pin set to high and VIN above the threshold VTH_UVLO+. It is driven to high impedance once VOUT trips the threshold VTH_PG+ for rising VOUT. The output is pulled to low level once VOUT falls below the threshold VTH_PG- . The output is as well pulled to low level in case the input voltage VIN falls below the undervoltage lockout threshold VTH_UVLO- or the device is disabled with EN = Low. With EN = High, the output is driven to high impedance state, once the load current falls below ~1 mA. In this case the PG comparator is turned off to achieve lowest quiescent current. PG will be triggered when a output voltage change is ongoing due to a change in VSEL pin levels if the new target is high enough to trigger the PG threshold.
9.3.4 Output Voltage Selection (VSEL1 - 4)
The TPS62745 does not require an external resistor divider network to program the output voltage. The device integrates a high impedance (typical 50 MΩ ) feedback resistor divider network which is programmed by the pins VSEL1-4. TPS62745 supports an output voltage range of 1.8 V to 3.3 V in 100-mV steps while the TPS627451 supports an output voltage range of 1.3 V to 2.8 V. The output voltage can be changed during operation and supports simple dynamic output voltage scaling; see the Application and Implementation section for further details. The output voltage is programmed according to Table 1 for TPS62745 and Table 2 for TPS627451.
9.3.5 Input Voltage Switch
There is an internal switch that connects the input voltage applied at pin VIN to the VIN_SW output. The switch can be used to connect an external voltage divider for an ADC monitoring to the input voltage. An enable pin EN_VIN_SW turns the switch on and off, making sure there is no current through that external voltage divider when not needed. A logic high level on EN_VIN_SW turns the switch on once the input voltage is above the undervoltage lockout threshold and the device is enabled. The switch can be used for other purposes as long as the current rating of 5 mA and its turn-on resistance is observed. An external voltage divider should be in a range of 10 kΩ to 100 kΩ. Larger values than 100 kΩ can be used as long as the input resistance and capacitance of the external circuit (e.g. ADC input) is observed.
9.4 Device Functional Modes
9.4.1 Soft Start
When the device is enabled, the internal reference is powered up and after the startup delay time t Startup_delay has expired, the device enters soft start, starts switching and ramps up the output voltage. During soft start the device operates with a reduced current limit, ILIM_softstart , of typical 1/5 of the nominal current limit. This reduced current limit is active during the soft start time tSoftstart. The current limit is increased to its nominal value, ILIMF, once the soft start time has expired or the power good comparator detects that the output voltage reached its target value.
9.5 VOUT Discharge
The VOUT pin has a discharge circuit to connect the rail to GND, once it is disabled. This feature prevents residual charge voltages on the output capacitor, which may impact proper power up of the systems connected to the converter. With the EN pin pulled to low, the discharge circuit at the VOUT pin becomes active. The discharge circuit on VOUT is also associated with the UVLO comparator. The discharge circuit becomes active once the UVLO comparator triggers and the input voltage VIN has dropped below the UVLO comparator threshold VTH_UVLO- (typical 2.9 V).
9.6 Internal Current Limit
The TPS62745 integrates a current limit on the high side, as well on the low side MOSFETs to protect the device against overload or short circuit conditions. The peak current in the switches is monitored cycle by cycle. If the high side MOSFET current limit is reached, the high side MOSFET is turned off and the low side MOSFET is turned on until the current decreases below the low side MOSFET current limit.