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ZHCSB86E November 2011 – October 2021 TPS62150 , TPS62150A , TPS62151 , TPS62152 , TPS62153

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

RGT|16
- MPQF119H

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

RGT|16
- QFND098T

訂購信息

7.5 Electrical Characteristics

over operating junction temperature (T_J = –40°C to 125°C), typical values at V_IN = 12 V and T_A = 25°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	NOM	MAX	UNIT
SUPPLY
V_IN	Input voltage range⁽¹⁾			3		17	V
I_Q	Operating quiescent current	EN = High, I_OUT = 0 mA, device not switching			17	30	μA
I_Q	Operating quiescent current	EN = High, I_OUT = 0 mA, device not switching	T_A = –40°C to +85°C		17	25	μA
I_SD	Shutdown current⁽²⁾	EN = Low			1.5	25	μA
I_SD	Shutdown current⁽²⁾	EN = Low	T_A = –40°C to +85°C		1.5	4	μA
V_UVLO	Undervoltage lockout threshold	Falling input voltage (PWM mode operation)		2.6	2.7	2.8	V
V_UVLO	Undervoltage lockout threshold	Hysteresis			200		mV
T_SD	Thermal shutdown temperature				160		°C
T_SD	Thermal shutdown hysteresis				20		°C
CONTROL (EN, DEF, FSW, SS/TR, PG)
V_H	High level input threshold voltage (EN, DEF, FSW)			0.9	0.65		V
V_L	Low level input threshold voltage (EN, DEF, FSW)				0.45	0.3	V
I_LKG	Input leakage current (EN, DEF, FSW)	EN = V_IN or GND; DEF, FSW = V_OUT or GND			0.01	1	μA
V_{TH_PG}	Power-good threshold voltage	Rising (%V_OUT)		92%	95%	98%
V_{TH_PG}	Power-good threshold voltage	Falling (%V_OUT)		87%	90%	94%
V_{OL_PG}	Power-good output low voltage	I_PG = –2 mA			0.07	0.3	V
I_{LKG_PG}	Input leakage current (PG)	V_PG = 1.8 V			1	400	nA
I_SS/TR	SS/TR pin source current			2.3	2.5	2.7	μA
POWER SWITCH
r_DS(on)	High-side MOSFET ON-resistance	V_IN ≥ 6 V			90	170	mΩ
	High-side MOSFET ON-resistance	V_IN = 3 V			120		mΩ
	Low-side MOSFET ON-resistance	V_IN ≥ 6 V			40	70	mΩ
	Low-side MOSFET ON-resistance	V_IN = 3 V			50		mΩ
I_LIMF	High-side MOSFET forward current limit⁽³⁾	V_IN = 12 V, T_A = 25°C		1.4	1.7	2.2	A
OUTPUT
I_{LKG_FB}	Input leakage current (FB)	TPS62150, V_FB = 0.8 V			1	100	nA
V_OUT	Output voltage range (TPS62150)	V_IN ≥ V_OUT		0.9		6.0	V
	DEF (output voltage programming)	DEF = 0 (GND)			V_OUT
	DEF (output voltage programming)	DEF = 1 (V_OUT)		V_OUT + 5%
	Initial output voltage accuracy⁽⁴⁾	PWM mode operation, V_IN ≥ V_OUT + 1 V		785.6	800	814.4	mV
		PWM mode operation, V_IN ≥ V_OUT + 1 V, T_A = –10°C to 85°C		788.0	800	812.8
		Power Save Mode operation, C_OUT = 22 μF		781.6	800	822.4
	Load regulation⁽⁵⁾	V_IN = 12 V, V_OUT = 3.3 V, PWM mode operation			0.05		%/A
	Line regulation⁽⁵⁾	3 V ≤ V_IN ≤ 17 V, V_OUT = 3.3 V, I_OUT = 1 A, PWM mode operation			0.02		%/V

(1) The device is still functional down to undervoltage lockout (see parameter V_UVLO).

(2) Current into AVIN+PVIN pins

(3) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Section 8.4.4).

(4) This is the accuracy provided at the FB pin for the adjustable V_OUT version (line and load regulation effects are not included). For the fixed voltage versions, the (internal) resistive divider is included.

(5) Line and load regulation depend on external component selection and layout (see Figure 9-16 and Figure 9-17).